Patents by Inventor John C. GOSS

John C. GOSS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit design verification in a hardware accelerated simulation environment using breakpoints
    Patent number: 10539614
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
  • Circuit design verification in a hardware accelerated simulation environment using breakpoints
    Patent number: 9939487
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
  • CIRCUIT DESIGN VERIFICATION IN A HARDWARE ACCELERATED SIMULATION ENVIRONMENT USING BREAKPOINTS
    Publication number: 20180059182
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 1, 2018
    Inventors: Rahul BATRA, Debapriya CHATTERJEE, John C. GOSS, Christopher R. JONES, Christopher M. RIEDL, John A. SCHUMANN, Karen E. YOKUM
  • CIRCUIT DESIGN VERIFICATION IN A HARDWARE ACCELERATED SIMULATION ENVIRONMENT USING BREAKPOINTS
    Publication number: 20170176529
    Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Rahul BATRA, Debapriya CHATTERJEE, John C. GOSS, Christopher R. JONES, Christopher M. RIEDL, John A. SCHUMANN, Karen E. YOKUM