Patents by Inventor John C. Hanner

John C. Hanner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6388891
    Abstract: A shelf assembly and system, which reduces the potential for accidental disruption of service or damage to neighboring transmission elements in a telecommunications network. The present invention operates to guide the transmission elements or fiber cables to and/or from a mounting position, and in or out from either side of electrical and/or optical telecommunications equipment. Fiber cables coupled at the mounting positions can be directed through reversible and removable fiber channels. Each fiber channel has a smooth surface and a radius of curvature, which provides an appropriate bend radius for guiding, routing, or bending the fiber cables into a fiber trough.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: May 14, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Dean R. Falkenberg, John C. Hanners, Edward T. Iwamiya
  • Patent number: 6128188
    Abstract: A self-balancing temperature control device for an integrated circuit (IC) includes a heat sink attached to the IC having thermomorphic fins or vanes. When the IC increases its heat output, the fins or vanes warm up and change their shape in a manner that increases the rate at which heat is removed from the IC.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: October 3, 2000
    Assignee: Credence Systems Corporation
    Inventor: John C. Hanners
  • Patent number: 6078187
    Abstract: A test head for an integrated circuit tester includes a set of wedge-shaped node cards, one for each terminal of the integrated circuit device under test (DUT). Each node card holds circuits for carrying out all test activities at one DUT terminal including generating and transmitting a test signal to the DUT and receiving and processing a response signal produced by the DUT. The test and response signals pass through an I/O terminal at a narrow end of the node card. A card frame having hemispherical inner and outer shells holds the node cards substantially therebetween with the I/O terminal of each card protruding through an aperture in the inner shell. A centroid distributor having substantially a hemispherical shaped surface nesting within the inner shell of the card frame holds a set of first terminals in contact with the node card I/O terminals. A set of conductors within the centroid distributor interconnect each first terminal with a corresponding second terminal on a flat surface of the distributor.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: June 20, 2000
    Assignee: Credence Systems Corporation
    Inventors: John C. Hanners, Charles A. Miller
  • Patent number: 6040691
    Abstract: A test head for an integrated circuit tester includes a horizontal base holding a motherboard. The motherboard distributes test instructions to an array of daughterboards mounted thereon, the daughterboards being radially distributed about a central vertical axis of the motherboard. Each daughterboard holds a set of node cards and includes data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the daughterboards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board. The interface board extends those conductive paths from the pads to terminals of the DUT.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: March 21, 2000
    Assignee: Credence Systems Corporation
    Inventors: John C. Hanners, Charles A. Miller, Dean Stanford
  • Patent number: 6016250
    Abstract: A self-balancing temperature control device for an integrated circuit (IC) includes a heat sink attached to the IC having thermomorphic fins or vanes. When the IC increases its heat output, the fins or vanes warm up and change their shape in a manner that increases the rate at which heat is removed from the IC.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: January 18, 2000
    Assignee: Credence Systems Corporation
    Inventor: John C. Hanners
  • Patent number: 5986447
    Abstract: A test head for an integrated circuit-tester includes a horizontal base holding a circular motherboard. The motherboard distributes input test instructions to an array of carrier boards mounted thereon, the carrier boards being radially distributed about a central vertical axis of the motherboard. Each carrier board holds a set of daughterboards, and each daughterboard holds a set of node cards. The carrier boards and daughterboards include data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the carrier boards extend downward through apertures in the base to contact pads on an interface board holding the DUT.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: November 16, 1999
    Assignee: Credence Systems Corporation
    Inventors: John C. Hanners, Charles A. Miller, Dean Stanford
  • Patent number: 4479079
    Abstract: The commutator of a DC motor is uniquely constructed to include at least one dead segment at least as wide as the associated brush (brushes). A silicon controlled rectifier (SCR) is arrranged in the circuit between the voltage source and said brush (brushes) to provide a switching means to automatically cut off current flow therethrough each time a brush passes over the dead segment. The current is reestablished by way of a gating means, which in the preferred embodiment is a variable frequency pulse generator.
    Type: Grant
    Filed: October 21, 1983
    Date of Patent: October 23, 1984
    Inventor: John C. Hanner
  • Patent number: 4247808
    Abstract: The commutator or commutators of a DC motor are uniquely arranged with a plurality of peripherally spaced, current carrying segments separated by relatively large, electrically dead, non-conducting spaces, each of the dead spaces being at least as wide in a peripheral direction as the corresponding width dimension of the brushes positioned adjacent thereto. A silicon controlled rectifier (SCR) is arranged in the circuit between the negative pole of the voltage source and the commutator input terminal and acts as a switch to automatically cut off current flow therethrough each time a brush leaves a commutator segment. The current is not re-established until the SCR is again gated, which time may be varied by a variable resistor/capacitor gating circuit.To prevent stoppage of the motor with the brushes of the commutator in a dead space a plurality of commutators are provided with the segments thereof staggered with relation to the first.
    Type: Grant
    Filed: January 11, 1978
    Date of Patent: January 27, 1981
    Inventor: John C. Hanner