Patents by Inventor John C. Krause
John C. Krause has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963643Abstract: A scrubbing tool for cleaning a surface that has a handle for holding by a user in a cleaning operation. The handle has a first connector. The scrubbing tool also has a cleaning head having a second connector configured to mate with the first connector in order to attach the cleaning head to the handle in an engaged position. The cleaning head is comprised entirely of a material configured to dissolve in water and has a cleaning agent.Type: GrantFiled: September 22, 2023Date of Patent: April 23, 2024Assignee: SCRUB DADDY, INC.Inventors: John Edward Lee O'Brien, Aaron C. Krause, Aleksandrs Titovs, Joe M. Vaccaro
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Patent number: 11944242Abstract: A scrubbing tool for cleaning a surface that has a handle for holding by a user in a cleaning operation. The handle has a first connector. The scrubbing tool also has a cleaning head having a second connector configured to mate with the first connector in order to attach the cleaning head to the handle in an engaged position. The cleaning head is comprised entirely of a material configured to dissolve in water and has a cleaning agent.Type: GrantFiled: May 3, 2023Date of Patent: April 2, 2024Assignee: SCRUB DADDY, INC.Inventors: John Edward Lee O'Brien, Aaron C Krause, Aleksandrs Titovs, Joe M Vaccaro
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Patent number: 7016971Abstract: A distributed computer system includes links and routing devices coupled between the links and routing frames between the links. Each of the routing devices includes a congestion control mechanism for detecting congestion at the routing device and responding to detected congestion by gradually reducing an injection rate of frames routed from the routing device.Type: GrantFiled: May 24, 2000Date of Patent: March 21, 2006Assignees: Hewlett-Packard Company, IBM Corporation, Compaq Computer Corporation, Adaptec, Inc.Inventors: Renato J. Recio, David J. Garcia, Michael R. Krause, Patricia A. Thaler, John C. Krause
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Patent number: 6882656Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.Type: GrantFiled: April 13, 2004Date of Patent: April 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David A. Brown, John C. Krause
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Patent number: 6870814Abstract: A link extender node is used to extend links between end nodes and/or routing nodes in a system area network. A connection includes a first link, coupling an end or routing node to a local port of a first link extender, a second link coupling the remote ports of first and second link extenders, and a third link coupling the local port of the second link extender to an end or routing node. The link extender includes link exception detection logic and transmits a this link bad command on the link generating the exception and transmits an other link bad command on the link not generating the exception.Type: GrantFiled: October 12, 1999Date of Patent: March 22, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David J. Garcia, John C. Krause, William J. Watson, David A. Brown, Richard W. Cutts, Jr., Melvin Kent Benedict
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Publication number: 20040190538Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.Type: ApplicationFiled: April 13, 2004Publication date: September 30, 2004Applicant: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David A. Brown, John C. Krause
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Patent number: 6765922Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.Type: GrantFiled: September 27, 2000Date of Patent: July 20, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David A. Brown, John C. Krause
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Patent number: 6728909Abstract: A multiprocessor or clustered system with processing elements communicatively interconnected transmits and receives data in the form of message packets. Certain of the message packets are either responding to earlier requests with the data, or are requests that the data of the packet be written at the destination. Each message packet has an initial portion that includes information about the packet, including what the data is carrying (i.e., data in response to an earlier request, or data to be written), the source and ultimate destination of the message packet. This information prevents errant data being written at the destination by determining if the source has “permission” to send such data to the destination. When a message packet carrying data is received, processing of the packet is started in parallel with continued reception of the data it carries by using the information contained in the initial portion to check the permissions.Type: GrantFiled: September 26, 2000Date of Patent: April 27, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David A. Brown, John C. Krause, Charles E. Peet
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Patent number: 6249756Abstract: An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.Type: GrantFiled: December 7, 1998Date of Patent: June 19, 2001Assignee: Compaq Computer Corp.Inventors: William Patterson Bunton, David A. Brown, David T. Heron, Charles Edward Peet, Jr., William Joel Watson, John C. Krause
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Patent number: 6175882Abstract: A system and technique of auto-configuring a first module to be in the same mode as a second module includes testing the frequency of a clock signal received from the second module to determine its mode of operation. The first module then auto-configures its ports to be in the same state as the second module. Additional test include the number of clock signals and symbol size to detect additional modes of operation. The first module is auto-configured as a result of the tests.Type: GrantFiled: December 7, 1998Date of Patent: January 16, 2001Assignee: Tandem Computers IncorporatedInventors: William P. Bunton, David A. Brown, John C. Krause, Charles E. Peet, Jr.
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Patent number: 6157967Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: December 30, 1997Date of Patent: December 5, 2000Assignee: Tandem Computer IncorporatedInventors: Robert W. Horst, William Edward Baker, Linda Ellen Zalzala, William Patterson Bunton, Richard W. Cutts, Jr., David J. Garcia, John C. Krause, Stephen G. Low, David Paul Sonnier, William Joel Watson, Patracia L. Whiteside
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Patent number: 6151689Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: December 9, 1996Date of Patent: November 21, 2000Assignee: Tandem Computers IncorporatedInventors: David J. Garcia, William Patterson Bunton, John Deane Coddington, John C. Krause, Susan Stone Meredith, David P. Sonnier, William Joel Watson, Linda Ellen Zalzala
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Patent number: 5914953Abstract: A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.Type: GrantFiled: June 7, 1995Date of Patent: June 22, 1999Assignee: Tandem Computers, Inc.Inventors: John C. Krause, David J. Garcia, Robert W. Horst, Geoffrey I. Iswandhi, David Paul Sonnier, William Joel Watson, Linda Ellen Zalzala
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Patent number: 5867501Abstract: A method of encoding data and commands as N-bit words includes using a first portion of the word to identify whether the word carries data or a command. In the case of a command, the command is in a second portion of the word. In the case of data, a part of the data is contained in the second portion of the word, while the remaining part of the data is encoded in the first portion of the word.Type: GrantFiled: June 7, 1995Date of Patent: February 2, 1999Assignee: Tandem Computers IncorporatedInventors: Robert W. Horst, John C. Krause
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Patent number: 5790776Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: August 4, 1998Assignee: Tandem Computers IncorporatedInventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, John C. Krause, Kenneth H. Porter, William Joel Watson, Linda Ellen Zalzala
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Patent number: 5751955Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Tandem Computers IncorporatedInventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, Daniel L. Fowler, Curtis Willard Jones, Jr., John C. Krause, Michael P. Simpson, William Joel Watson
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Patent number: 5751932Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Tandem Computers IncorporatedInventors: Robert W. Horst, William Edward Baker, Randall G. Banton, John Michael Brown, William F. Bruckert, William Patterson Bunton, Gary F. Campbell, John Deane Coddington, Richard W. Cutts, Jr., Barry Lee Drexler, Harry Frank Elrod, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Geoffrey I. Iswandhi, Douglas Eugene Jewett, Curtis Willard Jones, Jr., James Stevens Klecka, John C. Krause, Stephen G. Low, Susan Stone Meredith, Steven C. Meyers, David P. Sonnier, William Joel Watson, Patricia L. Whiteside, Frank A. Williams, Linda Ellen Zalzala
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Patent number: 5694121Abstract: A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input is kept waiting. Each input is provided an assigned bias value from which is developed the accumulated bias value that is compared with that of other inputs arbitrating for access to an output. The output selects one of the inputs, based upon the comparison, and the accumulated bias value of the selected input is diminished by the sum of the assigned bias values of the inputs participating in the arbitration, but not selected, while the accumulated bias values of the other participants are each increased by their corresponding assigned bias values.Type: GrantFiled: June 6, 1995Date of Patent: December 2, 1997Assignee: Tandem Computers IncorporatedInventors: John C. Krause, William J. Watson, David P. Sonnier, Robert W. Horst
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Patent number: 5631955Abstract: A method and apparatus for connecting remote options to a digital telephone base. Physical and communications protocols for connections and a flexible control scheme which can be as simple or elaborate as a given option requires are provided. The digital telephone includes an option bay connection, having a hierarchical control protocol. The option bay connection makes available several types of information, including: local analog audio, analog voice, digital voice, digital data and telephone control streams.Type: GrantFiled: May 15, 1995Date of Patent: May 20, 1997Assignee: Siemens Business Communication Systems, Inc.Inventors: Joel Q. Adams, David C. Black, William F. Dunn, Jr., Norman Endick, James B. Koehler, Michael K. Kounnas, John C. Krause, Diep N. Le, Larry A. Stell
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Patent number: 5574849Abstract: Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.Type: GrantFiled: June 7, 1995Date of Patent: November 12, 1996Assignee: Tandem Computers IncorporatedInventors: David P. Sonnier, Wiliam P. Bunton, Richard W. Cutts, Jr., James S. Klecka, John C. Krause, William J. Watson, Linda E. Zalzala