Abstract: A data processor controller comprising a first processor for generating data processor instructions at a first rate and an instruction multiplying circuit for receiving the data processor instructions at the first rate and being a arranged to multiply the instructions and forward the multiplied instructions to a data processor at a second rate substantially greater than the first rate is disclosed. The first processor outputs a stream of compounded data processor instructions and the multiplying circuit separates the compounded instructions into a single stream of individual instructions in a non-compounded format. Multiplication is effectively achieved by repeating both single and blocks of data processor instructions. The effective bandwidth between the first processor and the data processor is multiplied by the multiplying circuit which takes advantage of the different sizes of data pathways available between the first processor and the data processor.