Abstract: A data storage device comprising a storage media and a controller is disclosed. The controller is configured to receive a write command including a logical address and new data associated with the logical address, to write the new data to a new physical address on the storage media, and to remove old data associated with the logical address from an old physical address on the storage media, wherein the new physical address and the old physical address are different.

Abstract: A disk drive including a method for determining an amplitude for signal transmission over an interconnect is disclosed. The drive includes a processor that is coupled to a signal measurement circuit and is under the control of a program in conjunction with the signal measurement circuit to transmit a first signal to the host over a transmission medium at a first transmission frequency according to a first speed negotiation process, receive a second signal from the host at the first transmission frequency, determine a first voltage amplitude of the second signal, transmit a third signal to the host at a second transmission frequency according to a second speed negotiation process, receive a fourth signal from the host at the second transmission frequency, determine a second voltage amplitude of the fourth signal, and determine an approximate voltage loss in response to the first and second voltage amplitudes.

Abstract: A method for determining an amplitude for signal transmission over an interconnect is disclosed. The method includes transmitting a first signal to a host over a transmission medium at a first transmission frequency according to a first speed negotiation process and receiving a second signal from the host at the first transmission frequency. The method also includes measuring a first voltage amplitude of the second signal and transmitting a third signal to the host at a second transmission frequency according to a second speed negotiation process. The method further includes receiving a fourth signal from the host at the second transmission frequency, measuring a second voltage amplitude of the fourth signal, and determining an approximate voltage loss in response to the first and second voltage amplitudes.

Abstract: A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication in accordance with the SATA format with the host. The serial interface during the transmission of primitives in a pass-through phase, inserts pass-through information to the host within or outside of a Frame Information Structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.

Abstract: A disk drive is disclosed comprising a disk, a buffer memory, and control circuitry operable to receive a write command from a host, wherein the write command comprises write data and a write data address. Write EDC data is generated in response to the write data and the write data address, wherein the write data and the write EDC data are stored in the buffer memory. The write data is read from the buffer memory, and write check data is generated in response to the write data and the write data address. The write EDC data is read from the buffer memory and compared to the write check data to detect a write error. If the write error is not detected, the write data is written to the disk without writing the write EDC data to the disk.

Abstract: A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication with the host in accordance with the SATA format. The serial interface, after the transmission of a continued primitive, inserts pass-through information to the host within or outside of a frame information structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.

Abstract: A disk drive including a disk, a signal measurement circuit to measure amplitudes of signals received from the host, and a processor for controlling operations in the disk drive. The processor under the control of a program in conjunction with the signal measurement circuit: measures an amplitude of a signal from a host during a first speed negotiation process and determines if the amplitude of the signal from the host is above a pre-determined amplitude for the disk drive. If so, the processor commands the disk drive to transmit the signals to the host at the measured amplitude of the first speed negotiation process. However, if the amplitude is below the pre-determined amplitude for the disk drive, a second speed negotiation process is forced using a low frequency signal from the host and calculations are performed to determine appropriate transmit amplitudes for the interconnect.

Abstract: A disk drive is disclosed for connecting to a host, the host comprising loopback circuitry operable to loop a pattern received from the disk drive back to the disk drive. The disk drive comprises interface circuitry including a transmitter driver operable to transmit transmission signals at a transmission amplitude, and a receiver driver operable to receive reception signals. The transmitter driver is configured to transmit at an initial transmission amplitude, and a calibration pattern is transmitted to the host through the transmitter driver. The reception signals received by the receiver driver are monitored to detect a loopback pattern representing a loopback of the calibration pattern. The loopback pattern is processed to detect an error, and the transmission amplitude is adjusted in response to the error.

Abstract: An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead.

Abstract: An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead.

Abstract: A programmable output buffer has source/sink characteristics that may be programmed to match the capacitive load to be driven. The programmable output buffer comprises a plurality of individually-enableable unit buffers, and a programmable unit buffer driver control logic. By programming the control logic to enable only such unit buffers whose current handling contributions are necessary to drive the output buffer load capacitance, current spiking can be minimized. The unit buffers preferably are scaled so each can source or sink a different magnitude current relative to the other unit buffers, a range of output buffer current may be programmed in discrete current steps. The control logic preferably includes elements that delay delivery of an enabling signal to various of the unit buffers. In a cascade-up mode, the control logic sequentially delays enabling signals so that various of the required unit buffers are enabled sequentially, to minimize problems associated with current spiking.