Abstract: A programmable on-focal plane signal processor having analog to digital conversion, nonuniformity correction, gamma spike compensation all digitally performed on a single silicon substrate inside a dewar. The architecture supports time delay integration and spatial filtering to increase the signal to noise ratio of the focal plane array data. The processor has programmable coefficients which may be changed while the system is operating or eliminated. The architecture provides increased signal noise ratio for infrared data and decreases the output data bandwidth from the infrared focal plane array by two orders of magnitude.