Abstract: A dynamic signal generating circuit for exercising semiconductors and other electronic devices and circuits which includes first and second address selectors, first and second PROM address counters connected to said first and second address selectors respectively, first and second interval timer PROMs connected to said first and second address counters respectively, first and second output signal PROMs connected to said first and second interval PROMs respectively and means to connect said first output signal PROMs through clock and address drivers to a device under test and means to connect said second output signal PROMs through clock drivers to said device being tested and means connecting said first output PROMs through data drivers to said device being tested whereby said circuit controls a dynamic signal pattern system for exercising said semiconductors or other electronic devices and circuits.