Abstract: A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.

Abstract: A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.

Abstract: A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.

Abstract: A method and apparatus to switch between two audio streams without creating a clicking transient. A first serial audio stream is brought into a serial shift register. A series of samples of that audio stream are multiplied by reducing coefficients until a contribution of the first audio stream reaches zero. Then, a second serial audio stream is brought into the serial shift register. Increasing coefficients are applied to a series of samples until a contribution of the second audio stream is one.

Abstract: A method for recovering clock signals includes generating a media sync signal to synchronize processing of digital media, and generating a transmission reference clock signal to define a duration of a transaction through a packet-based data network. The media sync and transmission clock signals may have different frequency and phase. The media is sent to a slave node of the network. The media sync and transmission clock signals are correlated to generate phase correlation information, and the phase correlation information is also sent to the slave node. Accordingly, a relatively low cost and reliable clock recovery technique suitable for synchronizing media streams across a packet-based data network is disclosed.

Abstract: A method for recovering clock signals includes generating a media sync signal to synchronize processing of digital media, and generating a transmission reference clock signal to define a duration of a transaction through a packet-based data network. The media sync and transmission clock signals may have different frequency and phase. The media is sent to a slave node of the network. The media sync and transmission clock signals are correlated to generate phase correlation information, and the phase correlation information is also sent to the slave node. Accordingly, a relatively low cost and reliable clock recovery technique suitable for synchronizing media streams across a packet-based data network is disclosed.

Abstract: A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.

Abstract: An electrical power distribution system and automatic bus transfer switch therefor, consisting of two pairs of insulated gate bipolar transistors (IGBTs) connected in series in a back-to-back circuit configuration with respective semiconductor diodes connected across the current conducting terminals thereof so as to provide a static AC switch configuration which implements a fight-through bus transfer switch wherein only one pair of switches is rendered conductive at any one time, wherein one transistor and a diode across the other transistor of the same pair conduct in each half cycle of the AC power waveform, and thus provide power to one or more load(s) from either of two AC sources, a primary AC source or an alternate AC source.

Abstract: A digital test signal generator that provides for real-time parameter adjustment of digitally synthesized video test signals has a pair of test signal memories coupled one at a time via address and data multiplexers to a test signal synthesizer. Also coupled to the pair of test signal memories via the address and data multiplexers is a processor. The processor is coupled to one memory while the test signal synthesizer is coupled to the other. When a user changes a parameter at a front panel, the processor loads the one memory with new data representing the selected video test signal as modified by the parameter change. The processor than toggles the address and data multiplexers so that the one memory is coupled to the test signal synthesizer to generate the modified video test signal according to the changed parameter while the other memory is coupled to the processor ready to be loaded with data according to a next parameter change.

Abstract: A digital test signal generator includes the ability to adjust the SCH phase of the output test signal. A color frame reset pulse is generated at the beginning of each color frame of the output test signal. The color frame reset pulse is input to a direct digital signal synthesizer together with an SCH phase adjust signal to initialize the synthesizer with an SCH phase offset at the beginning of each color frame. By varying the amount of the SCH phase offset, the SCH phase in the output test signal is varied.

Abstract: A backplane connector system for electrically interconnecting an electronic module to a backplane assembly using a solder-free technique is described. A plurality of mating pads of conductive material are positioned on the surface of the backplane as a system interface. A corresponding series of plunger contacts are embedded in rows of cavities within a single connector body. At least one button spring having an elastic response to deformation is positioned within the cavities and touches the plunger contacts. The connector body, which has a variety of configurations, is attached to either the electronic module or to the backplane assembly. Upon installation of the electronic module into the backplane assembly, the plunger contacts depress into the button springs. The elastic response of the button springs holds the connection in compression and forms a compliant, solder-free, electrical interface.

Abstract: A test signal generator applies a test pattern to a device under test. The output of the device under test is displayed on a video picture monitor. The test signal generator inserts a cursor into the test pattern, the position of the cursor within the test pattern being variable. From the cursor the test signal generator also generates a trigger signal. The trigger signal may be used to trigger the horizontal sweep of a waveform display device to which the output of the device under device is input. By observing the picture monitor an operator may adjust the cursor to a position just prior to an anomaly in the displayed test pattern so that only that portion of the output waveform of the device under test in the vicinity of the cursor is displayed on the waveform display device.

Abstract: A television signal generator which is fully digital has digital data stored in PROMs, one PROM for each component of the desired encoded television signal corresponding to luminance data and chrominance data. A system clock allows a signal address generator to fetch data from the PROMs. The chrominance data from the PROMs is mixed with appropriate digital representations of a sinusoidal function and a phase offset and is added to the luminance data. The combined digital signal is converted to analog, filtered and output as the desired encoded television signal.

Abstract: A television signal generator which is fully digital has digital data stored in PROMs, one PROM for each component of the desired encoded television signal corresponding to luminance data and chrominance data. A system clock allows a signal address generator to fetch data from the PROMs. The chrominance data from the PROMs is mixed with appropriate digital representations of a sinusoidal function and a phase offset and is added to the luminance data. The combined digital signal is converted to analog, filtered and output as the desired encoded television signal.