Abstract: A flash memory file system logically divides at least a portion of the flash memory into memory fragments and headers associated with the memory fragments. The flash memory file system also includes a transaction information structure in support of transacted operations. The transaction information structure includes fields to indicate whether a transaction has begun, whether commitment of the transaction has begun, and whether commitment of the transaction has been completed. File system operations may be rolled back if a transaction was interrupted.

Abstract: In one embodiment of the present invention, a method includes setting an update to data of a memory to a valid status, and changing an original version of the data to a backup status.

Abstract: Adding a nonvolatile storage (e.g., a cache) to an associated memory array within a semiconductor nonvolatile memory may mitigate the access penalty that occurs in semiconductor nonvolatile memories, such as flash memories and flash devices. For example, in response to a memory access request, the cache may be accessed for data before accessing the memory array and the data may be selectively stored from the memory array into the cache. In another embodiment, an asynchronous access to a semiconductor nonvolatile memory may be converted into a synchronous access.

Abstract: A nonvolatile memory device may include circuitry to support the partitioning of the memory into two or more logical partitions. The two or more logical partitions may be accessible by two or more separate interfaces with different characteristics.

Abstract: A memory system including a programmable memory, such as a flash memory, may include a write buffer. A processor may generate and store a queue of commands to write a sequence of valid bytes in a reclaim operation. A controller in the memory system may perform the write commands in the write buffer without intervention by the processor.

Abstract: In one embodiment, a multilevel segmented memory device may be used to store persistent data in a first memory level and dynamic data in a second memory level. In the first level, data fragments may grow in an ascending order, and sequence tables may grow in a descending order. In the second level, object pointers may grow in a descending order, and data units grow in an ascending order.

Abstract: The same storage may be utilized to store both persistent and dynamic data in a processor-based system. In some embodiments, the storage may be a phase change memory. When data is to be stored, the memory manager determines whether the data is persistent. If the data is persistent it is managed in a fragmented fashion. Non-persistent or dynamic data is managed as a heap.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: In one embodiment of the present invention, a method includes setting an update to data of a memory to a valid status, and changing an original version of the data to a backup status.

Abstract: A program different than an operation system may be utilized to partially update an original image of system code. In one embodiment, operating system code may be adaptively stored and updated within a non-volatile storage device across at least two different memories into at least two code objects based on the relative utilization of the system code in the two code objects. Operating system patching or application and driver updates may be provided without re-writing an entire image of operating system code in some embodiments. The tuning of operating system code storage may be implemented based on a usage pattern of the operating system code on a device in some cases.

Abstract: A hardware comparator may be utilized to locate data in non-volatile memories such as flash memories. By using a hardware, instead of a software, approach, the access speed may be improved and the load on the unit that executes the software may be reduced.

Abstract: A non-volatile memory, such as a flash memory, may have improved speed when writing by providing direct memory access to a write buffer maintained in system memory. Because the write buffer in system memory may be relatively large, a sufficient buffer is available to the non-volatile memory to improve write performance. At the same time, the cost of the non-volatile memory is not prohibitively increased by providing an on-chip write buffer of substantial size.

Abstract: Adding a nonvolatile storage (e.g., a cache) to an associated memory array within a semiconductor nonvolatile memory may mitigate the access penalty that occurs in semiconductor nonvolatile memories, such as flash memories and flash devices. For example, in response to a memory access request, the cache may be accessed for data before accessing the memory array and the data may be selectively stored from the memory array into the cache. In another embodiment, an asynchronous access to a semiconductor nonvolatile memory may be converted into a synchronous access.

Abstract: Storing an application onto a system includes receiving the application, determining specifications of the system, and reorganizing the application in accordance with the specifications of the system so as to improve execution of the application. The reorganized application is stored on the system.

Abstract: A memory system including a programmable memory, such as a flash memory, may include a write buffer. A processor may generate and store a queue of commands to write a sequence of valid bytes in a reclaim operation. A controller in the memory system may perform the write commands in the write buffer without intervention by the processor.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an execute-in-place application) using an associated database. Within a flash memory, in one embodiment, an executable program may be separately stored in a non-fragmented manner from a resident database that includes program management information for use in an execution that does not involve a random access memory, saving time and resources.

Abstract: The same storage may be utilized to store both persistent and dynamic data in a processor-based system. In some embodiments, the storage may be a phase change memory. When data is to be stored, the memory manager determines whether the data is persistent. If the data is persistent it is managed in a fragmented fashion. Non-persistent or dynamic data is managed as a heap.

Abstract: There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Abstract: A multi-level cell memory may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.