Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A structure formed during processing of an integrated circuit. Two layers of photoresist are formed over a conductive layer to be patterned. The lower layer is thinner than the upper layer, and is dyed to have a lower transmittance. Both layers are used as a masking pattern for the underlying conductive layer.

Abstract: A method of forming vias in an interlevel dielectric structure of an integrated circuit, such that the aspect ratio of the vias is smaller than the aspect ratios of vias having a height equal to the thickness of the entire interlevel dielectric structure, and the integrated circuit formed according to such a method. Conductive elements are formed over an insulator. A first dielectric structure is formed over the conductive elements and over the insulator. The first dielectric structure contains a first dielectric, formed over the conductive elements and the insulator, and a planarizing dielectric, formed over the first dielectric to bulk fill the areas between the conductors. A thin layer of a second dielectric can be formed over the first dielectric and the planarization dielectric. Vias are patterned and etched in the first dielectric structure. The thickness of the first dielectric structure is such that the aspect ratios of the vias through it is close to, or less than, 1.

Abstract: Integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer.

Abstract: A method for fabricating conductive structures in integrated circuits. A conductive layer is formed over an underlying region in an integrated circuit. The conductive layer is then doped with impurities, and a thin amorphous silicon layer is formed over the conductive layer. A photoresist layer is then deposited and exposed to define a masking pattern. During exposure of the photoresist layer, the amorphous silicon layer acts as an anti-reflective layer. Portions of the photoresist layer are then removed to form a masking layer, and the insulating layer and amorphous silicon layer are then etched utilizing the masking layer to form conductive structures. During subsequent thermal processing, impurities from the conductive layer diffuse into the amorphous silicon layer causing the amorphous silicon layer to become conductive.

Abstract: A method of forming an integrated circuit wherein a planarization step is been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Abstract: A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A conductive structure for an integrated circuit. An amorphous silicon layer overlies a silicide layer atop a conductive polycrystalline silicon structure. An insulating layer overlies the overall structure formed by the three layers. An opening through the insulating layer also extends through the amorphous silicon layer to expose a portion of the silicide layer. An upper interconnect layer extends through the insulating layer and the amorphous silicon layer to make contact with the silicide layer.

Abstract: A photolithographic system wherein optical fiber routing is used to combine two or more ultraviolet light sources for reticle illumination.

Abstract: A method for patterning a reflective surface in an integrated circuit. A first photoresist layer is formed over a conductive layer in the integrated circuit. A second photoresist layer is then formed over the first photoresist layer, where the transmittance of the first photoresist layer is less than the transmittance of the second photoresist layer. The first and second photoresist layers are exposed to define a masking pattern, and portions of the first and second masking layers are then removed to form a mask which corresponds to the masking pattern. Finally, the conductive layer is patterned using the mask formed by the first and second photoresist layers.