Abstract: A method for detection of an orthogonal frequency division multiplex (OFDM) packet preamble is described. The method includes quantizing a real part and an imaginary part of each complex template value to a template index value, determining a plurality of non-zero template index values based on the quantization, receiving a signal including a plurality of samples, performing a plurality of first sums, where each first sum sums a sample subset of plurality of sample subsets, and assigning the plurality of non-zero template index values to the plurality of first sums. The method further includes performing a transposition of each first sum using the assigned non-zero template index value, performing a second sum, where the second sum is a complex weighted sum of the transposition of each first sum, and determining that the received signal comprises the OFDM packet preamble based on the complex weighed sum.

Abstract: A method and waveform handling apparatus for capturing and storing data waveforms and metadata for analysis. The method includes receiving waveform data and metadata, the waveform data corresponding to a demodulated data burst, creating a waveform data record from the received waveform data, associating the waveform data with corresponding metadata, and creating a metadata record from the corresponding metadata. The method allows the waveform data in the waveform data record to be stored in a first data repository and the corresponding metadata in the metadata record to be stored in a second data repository, the waveform data and the corresponding metadata accessible for analysis.

Abstract: A method and waveform handling apparatus for capturing and storing data waveforms and metadata for analysis. The method includes receiving waveform data and metadata, the waveform data corresponding to a demodulated data burst, creating a waveform data record from the received waveform data, associating the waveform data with corresponding metadata, and creating a metadata record from the corresponding metadata. The method allows the waveform data in the waveform data record to be stored in a first data repository and the corresponding metadata in the metadata record to be stored in a second data repository, the waveform data and the corresponding metadata accessible for analysis.

Abstract: A method and wireless communication device for tracking frequencies of transmitted burst signals. The method includes receiving a burst signal, determining a quality of the burst signal and a carrier frequency of the burst signal, demodulating the burst signal based upon the determined carrier frequency, determining a frequency offset of the burst signal based on the determined carrier frequency, and when the quality of the burst signal exceeds a threshold, calculating a drift window based on the determined frequency offset.

Abstract: A method and waveform handling apparatus for capturing and storing data waveforms and metadata for analysis. The method includes receiving waveform data and metadata, the waveform data corresponding to a demodulated data burst, creating a waveform data record from the received waveform data, associating the waveform data with corresponding metadata, and creating a metadata record from the corresponding metadata. The method allows the waveform data in the waveform data record to be stored in a first data repository and the corresponding metadata in the metadata record to be stored in a second data repository, the waveform data and the corresponding metadata accessible for analysis.

Abstract: A method and wireless communication device for tracking frequencies of transmitted burst signals. The method includes receiving a burst signal, determining a quality of the burst signal and a carrier frequency of the burst signal, demodulating the burst signal based upon the determined carrier frequency, determining a frequency offset of the burst signal based on the determined carrier frequency, and when the quality of the burst signal exceeds a threshold, calculating a drift window based on the determined frequency offset.

Abstract: A communication system (100) includes at least one digital signal processor (DSP) and a WAN driver (80) operating on a processor that is electrically coupled to a memory. The WAN driver (80) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated.

Abstract: A communication system (100) includes at least one digital signal processor (DSP) and a WAN driver (80) operating on a processor that is electrically coupled to a memory. The WAN driver (80) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated. A configuration controller (92) keeps track of the MIPs processing requirement of each task available for allocation across the plurality of DSPs and the maximum processing capability of each DSP of the plurality of DSPs in response to changes in configuration of the communication system (100).

Abstract: The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Abstract: There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block.

Abstract: A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

Abstract: A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

Abstract: An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed.

Abstract: A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals.

Abstract: A system and method for efficient operation of a digital signal processor allows execution of a noncoherent FSK demodulation process at the baud rate of the incoming signal. First and second signal detecting channels terminate at a summing junction. A signal sampler for applying a sampled signal to the first and second signal detecting channels. The first and second signal detecting channels each include, in series, a finite impulse response filter for filtering out energy outside a selected bandwidth, automatic gain control and a demodulator. The finite impulse response filter means for the second signal detecting channel further shifts the phase of the sampled signal in the second signal detecting channel approximately 90 degrees relative to the sampled signal in the first signal detecting channel. The demodulator in each signal detecting channel further includes first and second sampled signal transmission paths terminating in a multiplying junction.

Abstract: An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.