Abstract: A circuit comprises an amplifier and a bias circuit. The amplifier comprises an output transistor comprising a source electrode, a drain electrode, and a gate electrode. The bias circuit comprises: a first control loop configured to set a first quiescent bias for the output transistor based on a first value of a first control voltage and a second value of a second control voltage, wherein the first quiescent bias is configured to put the output transistor in an on state; and a second control loop configured to set a second quiescent bias for the output transistor based on the first value of the first control voltage and the second value of the second control voltage. The second quiescent bias is configured to put the output transistor in an off state and to increase an insertion loss of the amplifier when the output transistor is in the off state.

Abstract: A current mirror circuit having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation producing current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.

Abstract: A current mirror circuit having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation producing current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.

Abstract: A variable attenuator having: an input port; a semiconductor device having a control electrode for controlling carriers flowing between a first electrode and a second electrode, such control electrode being coupled to one of the first and second electrodes, one of the first and second electrodes being coupled to the input port and the other one of the first and second electrodes being coupled to a reference potential to form an active device characterized by such device having a resistivity in the device to the flow of carriers substantially constant when such device is fed through input port with a signal having a relatively small power level and having a resistivity in the device to the flow of carriers which is nonlinear when such device is fed through input port with a signal having a relatively large power level; and an output port coupled to one of the first and second electrodes coupled to the input port.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A limiter circuit includes a rectification circuit coupled to an input of the limiter circuit. The rectification circuit produces a voltage having a predetermined average level. The level is a function of an input signal fed to the input of the limiter circuit. A voltage divider circuit is coupled to the rectification circuit for producing an output voltage having a level proportional to the input signal. An enhancement mode field effect transistor has a gate electrode fed by the output voltage produced by the voltage divider circuit. The transistor has drain and source electrodes coupled to an output of the limiter circuit and a reference potential, respectively. A transmission line is coupled between the input of the limiter and the output of the limiter circuit. The transmission line has an electrical length n&lgr;/4, where &lgr; is the nominal operating wavelength of the limiter circuit and n is an odd integer.