Abstract: A clock signal failure detection and recovery circuit for use in a system utilizing multiple, redundant clock signals. Multiple clock source circuits generate a clock signal and a periodic sync pulse, which in turn are manipulated to produce a clock signal present pulse and a periodic clock pulse. The periodic clock pulse associated with one clock signal will clock the circuitry which monitors a clock signal present pulse associated with a different clock signal. In this way, the absence of a clock signal present pulse can still be clocked into the monitoring circuitry when that particular clock signal has failed. Each clock signal present pulse is compared to at least two other clock signal present pulses, and upon recognition of a predetermined number of inconsistencies between the compared clock signal present pulses, a clock signal error signal will be issued.

Abstract: Apparatus for avoiding ambiguous data in a multi-requestor computing system of the type wherein each of the requestors has its own dedicated cache memory. Each requestor has access to its own dedicated cache memory for purposes of ascertaining whether a particular data word is present in its cache memory and of obtaining that data word directly from its cache memory without the necessity of referencing main memory. Each requestor also has access to all other dedicated cache memories for purposes of invalidating a particular data word contained therein when that same particular data word has been written by that requestor into its own dedicated cache memory. Requestors and addresses in a particular cache memory are time multiplexed in such a way as to allow a particular dedicated cache memory to service invalidate requests from other requestors without sacrificing speed of reference or cycle time of the particular dedicated cache memory from servicing read requests from its own requestor.