Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.

Abstract: A computing platform includes an array of interconnected field programmable gate arrays (FPGAs), memory, and external input/output interfaces. The platform is in the form of a blade conforming to the Advanced Telecommunications Computing Architecture (ATCA) standard. The platform is especially useful for telecommunications and networking applications.

Abstract: A computing platform includes an array of interconnected field programmable gate arrays (FPGAs), memory, and external input/output interfaces. The platform is in the form of a blade conforming to the Advanced Telecommunications Computing Architecture (ATCA) standard. The platform is especially useful for telecommunications and networking applications.

Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.

Abstract: A digital system is provided for synthesizing individual voices of musical instruments, which may then be combined into a musical composition. The system for a single voice is comprised of means for solving a system of simultaneous finite difference equations, where time is represented by real time in the computations. Musical sounds of the voice can then be produced by repetitiously solving the difference equations that model the instrument in real time, using an array of elemental means named "universal processing elements" (UPEs) interconnected by a matrix to each other and to external input and output terminals, and varying the sounds by varying the parameters. Each UPE is capable of computing Y=A+(B.times.M) from pipelined bit-serial inputs. The difference equations model a general linear filter, a second-order linear filter, a nonlinear polynomial function, and a random number (noise) generating function.

Abstract: An array of universal processing elements (UPEs) may be interconnected through a switching matrix in response to control words which are in turn produced by a programmed digital computer in response to commands from a keyboard or a data file, thereby routing the outputs of selected UPEs to other UPEs for further processing and/or combining a sound stream in digital form. The matrix is comprised of both local and global conductors, the local ones being available to selected groups of UPEs. Each UPE is implemented as a digital multiplier, preferably with pipelining, and each UPE is comprised of a plurality of stages, preferably implemented with an adder for computing the sum of a plus the Boolean logic function [b.multidot.m+d.multidot.m] and a multiplexer for forming the function [b.multidot.+d.multidot.m], where a, b, d and m are bits of the respective two's complement number A, B, D and M, whereby the entire array of stages in a UPE computes A+[B.times.M+D.times.(1-M)].

Abstract: A monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V.sub.dd) by a power-down p-channel MOS transistor. Each of the cMOS inverters is comprised of a first p-channel MOS transistor in source-drain-drain-source series with an n-channel MOS transistor. Two signal-pass n-channel MOS transistors are provided, one a signal-pass transistor connected as a series switch in a first signal (d) line to the input terminal of one cMOS inverter and the output terminal of the other cMOS inverter, and the other a signal-pass transistor connected as a series switch in a second complement signal (d) line to the input terminal of the other cMOS inverter and the output terminal of the one cMOS inverter.