Patents by Inventor John C. Weast
John C. Weast has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200210338Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 26, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Joydeep Ray, Narayan Srinivasa, Feng Chen, Ben J. Ashbaugh, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Eriko Nurvitadhi, Balaji Vembu, Altug Koker
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Publication number: 20200210472Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.Type: ApplicationFiled: November 26, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: BARNAN DAS, MAYURESH M. VARERKAR, NARAYAN BISWAL, STANLEY J. BARAN, GOKCEN CILINGIR, NILESH V. SHAH, ARCHIE SHARMA, SHERINE ABDELHAK, PRANEETHA KOTHA, NEELAY PANDIT, JOHN C. WEAST, MIKE B. MACPHERSON, DUKHWAN KIM, LINDA L. HURD, ABHISHEK R. APPU, ALTUG KOKER, JOYDEEP RAY
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Publication number: 20200202480Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.Type: ApplicationFiled: November 26, 2019Publication date: June 25, 2020Applicant: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Joydeep Ray
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Patent number: 10690511Abstract: Technologies for managing sensor anomalies in a compute system include determining whether sensor data received from a first sensor is anomalous based on sensor data from another sensor and a correlation rule. The correlation rule defines an excepted correlation between the first sensor data and the second sensor data. If the correlation between the first sensor data and the second sensor data is not observed, the first sensor data may be deemed anomalous. If so, the first sensor data may be verified using another sensor or other correlation. If the first sensor is determined to be malfunctioning, the compute system may mitigate the loss of the first sensor by using another sensor in its place.Type: GrantFiled: December 26, 2015Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Tobias M. Kohlenberg, Brian D. Johnson, John C. Weast
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Publication number: 20200020070Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Applicant: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
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Patent number: 10521349Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 15, 2019Date of Patent: December 31, 2019Assignee: INTEL CORPORATIONInventors: Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Joydeep Ray, Narayan Srinivasa, Feng Chen, Ben J. Ashbaugh, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Eriko Nurvitadhi, Balaji Vembu, Altug Koker
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Patent number: 10496697Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.Type: GrantFiled: September 6, 2018Date of Patent: December 3, 2019Assignee: INTEL CORPORATIONInventors: Barnan Das, Mayuresh M. Varerkar, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray
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Patent number: 10497084Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.Type: GrantFiled: April 24, 2017Date of Patent: December 3, 2019Assignee: INTEL CORPORATIONInventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Joydeep Ray
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Patent number: 10489877Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.Type: GrantFiled: April 24, 2017Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
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Patent number: 10484756Abstract: Technologies for presenting an advertisement on a media consumption device includes receiving a request to seek past a commercial included in media content played on the media consumption device, determining an advertisement based on the commercial, and presenting the advertisement to a user of the media consumption device during performance of the requested seek function. The advertisement may be, for example, an extracted frame or image of the commercial and may include a logo or phrase associated with a product or service advertised in the commercial. Similar technologies related to a media content distribution system are also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: November 19, 2019Assignee: Intel CorporationInventor: John C. Weast
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Publication number: 20190304054Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
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Publication number: 20190304053Abstract: Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
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Publication number: 20190295211Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.Type: ApplicationFiled: April 8, 2019Publication date: September 26, 2019Applicant: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Kamal Sinha, Joydeep Ray, Balaji Vembu, Sanjeev Jahagirdar, Vasanth Ranganathan, Dukhwan Kim
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Publication number: 20190266351Abstract: Technologies for displaying public and private images includes a display device and one or more user viewing devices. The display device is configured to display or generate a personalized image or video that is viewable by an authorized user viewing device and not viewable by unauthorized viewing devices. To facilitate the display of the personalized images, the display device and the user viewing device(s) may negotiate a display protocol to be used by the display device to display the personalized image in a private manner. In some embodiment, the display device may also display a public image or video that is viewable by unauthorized viewing devices and/or individuals without viewing devices.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Inventors: John C. Weast, Joshua Boelter
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Patent number: 10380375Abstract: Technologies for displaying public and private images includes a display device and one or more user viewing devices. The display device is configured to display or generate a personalized image or video that is viewable by an authorized user viewing device and not viewable by unauthorized viewing devices. To facilitate the display of the personalized images, the display device and the user viewing device(s) may negotiate a display protocol to be used by the display device to display the personalized image in a private manner. In some embodiment, the display device may also display a public image or video that is viewable by unauthorized viewing devices and/or individuals without viewing devices.Type: GrantFiled: November 24, 2014Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: John C. Weast, Joshua Boelter
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Publication number: 20190243764Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 15, 2019Publication date: August 8, 2019Applicant: Intel CorporationInventors: Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Joydeep Ray, Narayan Srinivasa, Feng Chen, Ben J. Ashbaugh, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Eriko Nurvitadhi, Balaji Vembu, Altug Koker
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Publication number: 20190222905Abstract: Technologies for presenting an advertisement on a media consumption device includes receiving a request to seek past a commercial included in media content played on the media consumption device, determining an advertisement based on the commercial, and presenting the advertisement to a user of the media consumption device during performance of the requested seek function. The advertisement may be, for example, an extracted frame or image of the commercial and may include a logo or phrase associated with a product or service advertised in the commercial. Similar technologies related to a media content distribution system are also disclosed.Type: ApplicationFiled: August 21, 2018Publication date: July 18, 2019Inventor: John C. Weast
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Publication number: 20190206020Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.Type: ApplicationFiled: November 21, 2018Publication date: July 4, 2019Applicant: Intel CorporationInventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
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Publication number: 20190197650Abstract: Systems and methods for determining a foreground application and at least one background application from multiple graphics applications executing within an execution environment are disclosed. Pixel data rendered by the foreground application may be displayed in the execution environment while a rendering thread of the background application may be paused.Type: ApplicationFiled: June 11, 2011Publication date: June 27, 2019Inventors: Tao Zhao, John C. Weast, Brett P. Wang
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Patent number: 10304154Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.Type: GrantFiled: April 24, 2017Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Kamal Sinha, Joydeep Ray, Balaji Vembu, Sanjeev Jahagirdar, Vasanth Ranganathan, Dukhwan Kim