Abstract: This invention provides a boarding aid [40] for small boats such as a trailer boats [57] which has a rigid stirrup assembly [59] incorporating a foot support [46] which pivots about a transverse axle [44] for the bow roller [56] between an on-deck stowed position to a deployed position at which it is stably supported by abutment against a stop [47] associated with and spaced from the axle [44]. The axle [44] and the stop [47] are part of a support frame assembly [58] which mounts to the boat's foredeck [48]. When the rigid stirrup assembly [59] pivots to its deployed position it is held stably by the abutment [47] in a position at which the foot support [46] is below and forwardly of the bow roller [56]. The boat is also provided with opposed bow rails [50, 51] which may be gripped to enable a user to elevate themselves from the foot support, onto the foredeck [48].

Abstract: This invention provides a boarding aid for small boats such as a trailer boats which has a rigid stirrup assembly incorporating a foot support which pivots about a transverse axle for the bow roller between an on-deck stowed position to a deployed position at which it is stably supported by abutment against a stop associated with and spaced from the axle. The axle and the stop are part of a support frame assembly which mounts to the boat's foredeck. When the rigid stirrup assembly pivots to its deployed position it is held stably by the abutment in a position at which the foot support is below and forwardly of the bow roller. The boat is also provided with opposed bow rails which may be gripped to enable a user to elevate themselves from the foot support, onto the foredeck.

Abstract: Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.

Abstract: Methods for designating target locations for circuit elements to be implemented in a programmable system. A target system is divided into blocks at various levels of hierarchy, with each block within the same higher-level block having a different identifier. A user can specify a desired location for a circuit element at any or all of these levels of hierarchy. Preferably, a desired location is specified using a single location constraint comprising a string of identifiers separated by delimiters. In one embodiment, a uniform coordinate system is applied to all blocks at a given level, even in a non-uniform programmable array. In this embodiment, a non-uniform array of logic blocks is divided into tiles, and a uniform coordinate system is applied to the tiles. Thus, any tile in the array can be addressed using a uniform coordinate system, regardless of the nature of the logic blocks comprising the tile.

Abstract: A complete logic family which is SEU immune is constructed, using logic/circuit design techniques, to recover from an SEU, regardless of the shape of the upsetting event. The logic family provides a redundancy of data to be used to restore data lost by an SEU. Two transistor networks are used, a p-channel network and an n-channel network. Each transistor network consists of a plurality of input transistors and a feedback transistor. The feedback transistor is sized to be weak compared to the input transistors. The transistor networks are designed to either resist an SEU or to shutdown until the SEU is over and then the network which is not shutdown will restore the data of the network that was hit by the SEU. The logic family can prevent glitch propagation from an upset node and can be implemented in a standard, commercial CMOS process without any additional processing steps. The logic family includes but is not limited to an Inverter, 2-input Nand, 2-input Nor, 3-input OrNand and a 3-input AndNor.

Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current.