Abstract: In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.

Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.

Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.

Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.

Abstract: An integrated circuit (IC) package includes a die having a interface region situated on a surface of the die. The interface region is configured to be exposed to an environment of the IC package. The IC package also includes a metal wall mounted on the surface of the die that circumscribes the interface region and extends from the surface of the die to a wall height. The metal wall has a first region and a second region that is stacked on the first region, the first region having a first thickness and the second region having a second thickness. The second thickness is greater than the first thickness. The IC package further includes a molding encasing a remaining portion of the die. The molding has a height that extends from the surface of the die to a level that is less than the wall height of the metal wall.

Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

Abstract: A semiconductor die includes a semiconductor surface including circuitry electrically connected to top-level bond pads exposed on a top surface of the semiconductor die, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads. There is solder on at least the inner bond pads. A ring structure is positioned around a location of at least the inner bond pads.

Abstract: In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.

Abstract: An electronic package includes an electronic component including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the electronic package, and a mold compound covering the electronic component and partially covering the leads. Each of the leads include an exposed bottom face coplanar with a bottom surface of the mold compound and an exposed end face coplanar with one of a plurality of side surfaces of the mold compound. For at least some of the leads, the exposed end face includes a narrow portion forming a concave recess, the narrow portion being between top and bottom edges of the exposed end face.

Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.

Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.

Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.