Abstract: A computer system having a cache for providing data to the system's processing unit(s), wherein the cache controller selectively aborts speculative accesses to its data array. The cache initiates a transfer of data by speculatively transmitting an associated address to the data array, and the data transfer is aborted in response to an intervening determination that the data is to be provided by another source, e.g., by the system memory device (a cache miss) or, in a multi-processor computer wherein the cache is an L3 cache supporting several processing units, by another processing unit which holds the data in a modified state. The data array is arranged in rows and columns, and accessed using a row address strobe (RAS) signal and a column address strobe (CAS) signal. The cache initiates the data transfer by driving a RAS signal associated with the address, and the data transfer is aborted prior to driving a CAS signal associated with the address.

Abstract: A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in a data processing system comprising at least one processor having an integrated controller, a cache external to the at least one processor, and an interface between the at least one processor and the external cache. The external cache includes a tag array and a data array. Standard synchronous static Random Access Memory (RAM) is used for the tag array, while synchronous burst made static RAM is used for the data array. The interface includes a shared address bus, a load address connection and an increment address connection. A cache line load/store operation is executed by placing an address for the operation on the shared address bus, and latching the address with the external cache using a signal from the load address connection.

Abstract: A logical bus architecture implements by active devices the functions performed by a physical address/command bus in the context of a multiple processing unit computer system. The logical bus eliminates the electrical loading, and associated frequency limitations, characterizing physical address/command buses as the number of system resources, processing units, connected to the bus increase. Address/command buses from the processing units are individually or in groups connected to ports of an address rebroadcast device. The device also receives bus master information from the computer system arbiter. Since the arbiter information is available before the actual transmission of signals over the address/command buses of the various processing units, bidirectional signal paths in the address rebroadcast device are selectively configured to match the master-slave signal flow between processing units as defined by the arbiter.