Abstract: A method for determining between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of at least three origins based on the selected pairs of data sets.

Abstract: A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.

Abstract: A method for determining the offset between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of the at least three origins based on the said selected pairs of said data sets.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator which may employ a graded band gap disposed adjacent said grid electrode, and a floating gate disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.

Abstract: A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node.

Abstract: A method for managing stepper operations required during the manufacturing of an integrated circuit die having at least one known defect, as determined by inspection, comprises the steps of determining, based upon an analysis of the connectivity and defect information relating to the die having at least one known defect a probability of failure to each at least one known defect and eliminating from stepper operations any die having at least one fatal defect.

Abstract: A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory.

Abstract: An improved method of programming flash EEPROM devices is provided, wherein the time required to write a plurality of data bytes to a flash EEPROM device with verification is substantially reduced. The disclosed method significantly reduces the effects of the settling times on the overall program-verification cycle by performing row verification of the programmed data bytes instead of the byte verification associated with conventional verification operations.

Abstract: A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided that applies a first erase voltage to the control gates of selected floating gate memory cells of the array to prevent erasure of the selected floating gate memory cells and a second erase voltage to the control gates of the remaining floating gate memory cells of the array to permit erasure of the remaining floating gate memory cells in a sector erase mode of operation. The decoder is also preferably capable of supplying the second erase voltage to the control gates of each of the floating gate memory cells in a bulk erase mode of operation.

Abstract: A flash EPROM cell may be erased by placing a negative voltage on the control gate of a flash EPROM cell having spaced apart source and drain regions in a semiconductor substrate, and having a floating gate, a control gate and a sidewall gate, while biasing the drain at a positive voltage.

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.