Patents by Inventor John Charles Robinson

John Charles Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11624775
    Abstract: Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 11, 2023
    Assignee: KLA Corporation
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Patent number: 11614480
    Abstract: A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 28, 2023
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Publication number: 20220390506
    Abstract: A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 8, 2022
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Publication number: 20220390505
    Abstract: Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Application
    Filed: July 9, 2021
    Publication date: December 8, 2022
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Publication number: 20220307990
    Abstract: A die screening system may receive die-resolved metrology data for a population of dies on one or more samples from the one or more in-line metrology tools after one or more fabrication steps, where the die-resolved metrology data includes images generated using one or more measurement configurations of the one or more in-line metrology tools. In this way, the die-resolved metrology data provides many measurement channels per die, where a particular measurement channel includes data from a particular pixel of a particular image. The controller may then generate screening data for the population of dies from the die-resolved metrology data, where the screening data includes a subset of the plurality of measurement channels of the die-resolved metrology data, and screen the plurality of dies into two or more disposition classes including at least outlier dies based on variability in the screening data.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 29, 2022
    Inventors: John Charles Robinson, Stilian Pandev, Shifang Li, Mike Von Den Hoff, Justin Lach, Barry Saville, David W. Price, Robert J. Rathert, Chet V. Lenox, Thomas Groos, Oreste Donzella
  • Patent number: 11293970
    Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 5, 2022
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Kara L. Sherman, John Charles Robinson, Mike Von Den Hoff, Barry Saville, Robert Cappel, Oreste Donzella, Naema Bhatti, Thomas Groos, Teng-Song Lim, Doug Sutherland
  • Publication number: 20210215753
    Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.
    Type: Application
    Filed: November 23, 2020
    Publication date: July 15, 2021
    Applicant: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Kara L. Sherman, John Charles Robinson, Mike Von Den Hoff, Barry Saville, Robert Cappel, Oreste Donzella, Naema Bhatti, Thomas Groos, Teng-Song Lim, Doug Sutherland
  • Patent number: 10466596
    Abstract: The present disclosure is directed to a method of determining at least one correctable for a process tool. In an embodiment, the method includes the steps of: measuring one or more parameter values at one or more measurement locations of each field of a selection of measured fields of a wafer; estimating one or more parameter values for one or more locations of each field of a selection of unmeasured fields of the wafer; and determining at least one correctable for a process tool based upon the one or more parameter values measured at the one or more measurement locations of each field of the selection of measured fields of the wafer and the one or more parameter values estimated for the one or more locations of each field of the selection of unmeasured fields of the wafer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 5, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Bill Pierson, Ramkumar Karur-Shanmugam, Chin-Chou Huang, Ady Levy, John Charles Robinson
  • Patent number: 10409171
    Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 10, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Michael E. Adel, Amnon Manassen, William Pierson, Ady Levy, Pradeep Subrahmanyan, Liran Yerushalmi, DongSub Choi, Hoyoung Heo, Dror Alumot, John Charles Robinson
  • Publication number: 20180253017
    Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.
    Type: Application
    Filed: January 10, 2018
    Publication date: September 6, 2018
    Inventors: Michael E. Adel, Amnon Manassen, William Pierson, Ady Levy, Pradeep Subrahmanyan, Liran Yerushalmi, DongSub Choi, Hoyoung Heo, Dror Alumot, John Charles Robinson
  • Publication number: 20150241790
    Abstract: The present disclosure is directed to a method of determining at least one correctable for a process tool. In an embodiment, the method includes the steps of: measuring one or more parameter values at one or more measurement locations of each field of a selection of measured fields of a wafer; estimating one or more parameter values for one or more locations of each field of a selection of unmeasured fields of the wafer; and determining at least one correctable for a process tool based upon the one or more parameter values measured at the one or more measurement locations of each field of the selection of measured fields of the wafer and the one or more parameter values estimated for the one or more locations of each field of the selection of unmeasured fields of the wafer.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Applicant: KLA-Tencor Corporation
    Inventors: Bill Pierson, Ramkumar Karur-Shanmugam, Chin-Chou Huang, Ady Levy, John Charles Robinson
  • Publication number: 20140303912
    Abstract: Inline yield monitoring may include the use of one or more modules of algorithmic software. Inline yield monitoring may include the use of two related algorithmic software modules such as a learning and a prediction module. The learning module may learn critical PET (parametric electrical test) parameters from data of probe electrical test yields and PET attribute values. The critical PET parameters may best separate outliers and inliers in the yield data. The prediction module may use the critical PET parameters found by the learning module to predict whether a wafer is an inlier or an outlier in a probe test classification.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 9, 2014
    Applicant: KLA-Tencor Corporation
    Inventors: Saibal Banerjee, Sonu Maheshwary, John Charles Robinson, Dale Legband