Abstract: Systems and techniques are generally described for selecting a machine learning model for compression artifact removal and resolution upscaling of video streaming data. In various examples, a system or method receives a stream of video data, determines a category of the stream of video data based at least partially upon a compression level of the stream of video data, selects weights for a machine learning model based upon the category, and executes the machine learning model with the selected weights to remove compression artifacts in the stream of video data and upscale a resolution of the stream of video data.

Abstract: Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.

Abstract: Systems and techniques are generally described for selecting a machine learning model for compression artifact removal and resolution upscaling of video streaming data. In various examples, a system or method receives a stream of video data, determines a category of the stream of video data based at least partially upon a compression level of the stream of video data, selects weights for a machine learning model based upon the category, and executes the machine learning model with the selected weights to remove compression artifacts in the stream of video data and upscale a resolution of the stream of video data.

Abstract: Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.