Patents by Inventor John Chaves

John Chaves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12326811
    Abstract: In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: June 10, 2025
    Assignee: STRATUS TECHNOLOGIES IRELAND LTD.
    Inventors: Andrew Alden, Chester Pawlowski, Christopher Cotton, John Chaves
  • Publication number: 20240176739
    Abstract: In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: STRATUS TECHNOLOGIES IRELAND LTD.
    Inventors: Andrew Alden, Chester Pawlowski, Christopher Cotton, John Chaves
  • Publication number: 20030043110
    Abstract: Disclosed herein is a personal mobile display that operate in collaboration with a host computer system that include a processor for executing PC compatible application programs capable of generating and displaying a plurality of operational functions and data in response to user specified input. The host system also includes a wireless data transceiver capable of communicating and exchanging application or system commands and data between the host computer and portable display tablet. The portable display tablet comprises a graphics display panel, a micro-controller, and a wireless transceiver to provide short-range communication between the host computer system and portable display tablet. The micro-controller of the portable display tablet executes a control program to process the commands and data received from the host computer via the wireless transceiver and provides the resultant application window, template, or graphical display data to the graphics display panel.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 6, 2003
    Applicant: AirSpeak
    Inventors: John Chaves, Glenn Perkins, Chuck Robinson