Abstract: In a computer data storage system configured for patching Read Only Memory (ROM) by remapping data sections, the ROM containing a token to define the start of each one of the data sections and a patch existing for at least one of the data sections, the patch providing additional data at the start of the data section; whereby the patch is included in one of the data sections when an access to one of the data sections is initiated at the token. The patch further optionally replaces at least a part of one of the data sections. The patch may be in writeable memory and if so, the ROM appears writeable thereby. The indicator will normally be a software No Operation or non-destructive instructive, since a No Operation instruction (NOP) causes a one cycle pause in the processor and allows time for the patch to be smoothly integrated.

Abstract: Translating between physical and logical (or virtual) address spaces occurs autonomously using information decoded by an address mode translator from command bits within a host CPU issued command. The translator communicates with a hard disc controller unit local microprocessor or microcontroller and controller unit task registers. A host CPU issued command interrupts the local microprocessor and activates the address mode translator by writing to an appropriate controller unit task register using indirect addressing. The address mode translator preferably provides four algorithms, with algorithm selection occurring autonomously according to the decoded command bits. The algorithms provide physical block address to physical CHS cylinder-head-sector conversion, logical CHS to logical block address conversion, and also provide divide and multiply functions, useful for disc caching.

Abstract: A mechanism determines at least an approximation of output load coupled to a programmable output buffer, and then programs the buffer to source/sink an amount of output current appropriate to the load to be driven. The mechanism includes a load recognition unit, an optional signal conditioner, and a reconfiguration logic module. In interface-governed applications, the load recognition unit senses an interface bit (AT Attachment interface), or causes the output buffer to act as a master unit that polls the interface connection to determine the number of attached loads (SCSI interface). The recognition unit then outputs a signal that may be conditioned before being input to a reconfiguration logic module that outputs appropriate control signals that program the buffer. Alternatively, the load recognition unit may measure the shunt capacitance associated with the load by using a reference current source and an analog/digital converter.