Patents by Inventor John Christopher Arnold
John Christopher Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378258Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Ruilong Xie, Anthony I. Chou, Brent A. Anderson, John Christopher Arnold, Junli Wang, Kai Zhao, Terence Hook, Julien Frougier, Xuefeng Liu
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Publication number: 20230215767Abstract: A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and between the first and second source-drain regions. Also included are a front side wiring network, having a plurality of front side wires, on a front side of the field effect transistor; a front side conductive path electrically interconnecting one of the front side wires with the first source-drain region; a back side power rail, on a back side of the FET; and a back side contact electrically interconnecting the back side power rail with the second source-drain region. A dielectric liner and back side dielectric fill are on a back side of the gate adjacent the back side contact, and they electrically confine the back side contact in a cross-gate direction.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: Ruilong Xie, Kisik Choi, Brent A Anderson, Lawrence A. Clevenger, John Christopher Arnold
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Publication number: 20230207553Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Inventors: Ruilong Xie, Kisik Choi, Somnath Ghosh, Sagarika Mukesh, Albert Chu, Albert M. Young, Balasubramanian S. Pranatharthiharan, Huiming Bu, Kai Zhao, John Christopher Arnold, Brent A. Anderson, Dechao Guo
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Patent number: 11688636Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.Type: GrantFiled: June 18, 2021Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Somnath Ghosh, Karen Elizabeth Petrillo, Cody J. Murray, Ekmini Anuja De Silva, Chi-Chun Liu, Dominik Metzler, John Christopher Arnold
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Publication number: 20230084739Abstract: A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.Type: ApplicationFiled: September 10, 2021Publication date: March 16, 2023Inventors: Dominik Metzler, SOMNATH GHOSH, John Christopher Arnold, Ekmini Anuja De Silva
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Publication number: 20220406657Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: SOMNATH GHOSH, Karen Elizabeth Petrillo, Cody J. Murray, Ekmini Anuja De Silva, Chi-Chun LIU, Dominik METZLER, John Christopher Arnold
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Publication number: 20220262636Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: ApplicationFiled: March 7, 2022Publication date: August 18, 2022Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Patent number: 11302533Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: GrantFiled: February 22, 2021Date of Patent: April 12, 2022Assignee: Tessera, Inc.Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Patent number: 11195995Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.Type: GrantFiled: January 6, 2020Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
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Patent number: 11189527Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.Type: GrantFiled: March 23, 2020Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Timothy Mathew Philip, Sagarika Mukesh, Dominik Metzler, Ashim Dutta, John Christopher Arnold
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Patent number: 11189528Abstract: A method is presented for constructing interconnects by employing a subtractive etch process. The method includes forming a plurality of first conductive lines within an interlayer dielectric, depositing dielectric layers over the plurality of first conductive lines, depositing a photoresist layer over the dielectric layers, patterning the photoresist layer to create vias to top surfaces of one or more of the plurality of first conductive lines, and depositing a conductive material such that the conductive material fills the vias and provides for a sheet of metal for second conductive lines formed above the first conductive lines.Type: GrantFiled: April 22, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Christopher Arnold, Balasubramanian S. Pranatharthi Haran, Takeshi Nogami
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Publication number: 20210335665Abstract: A method is presented for constructing interconnects by employing a subtractive etch process. The method includes forming a plurality of first conductive lines within an interlayer dielectric, depositing dielectric layers over the plurality of first conductive lines, depositing a photoresist layer over the dielectric layers, patterning the photoresist layer to create vias to top surfaces of one or more of the plurality of first conductive lines, and depositing a conductive material such that the conductive material fills the vias and provides for a sheet of metal for second conductive lines formed above the first conductive lines.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: John Christopher Arnold, Balasubramanian S. Pranatharthi Haran, Takeshi Nogami
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Publication number: 20210296118Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer; and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.Type: ApplicationFiled: March 19, 2020Publication date: September 23, 2021Inventors: Devika Sil, Ashim Dutta, Yann Mignot, John Christopher Arnold, Daniel Charles Edelstein, Kedari Matam, Cornelius Brown Peethala
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Publication number: 20210296169Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Timothy Mathew Philip, Sagarika Mukesh, Dominik Metzler, Ashim Dutta, John Christopher Arnold
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Publication number: 20210210679Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
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Publication number: 20210183653Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: ApplicationFiled: February 22, 2021Publication date: June 17, 2021Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Patent number: 10930504Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: GrantFiled: November 13, 2019Date of Patent: February 23, 2021Assignee: Tessera, Inc.Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Publication number: 20200083045Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: John Christopher ARNOLD, Sean D. BURNS, Yann Alain Marcel MIGNOT, Yongan XU
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Patent number: 10559467Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: GrantFiled: June 6, 2018Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES COPORATIONInventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Publication number: 20180286682Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Inventors: John Christopher ARNOLD, Sean D. BURNS, Yann Alain Marcel MIGNOT, Yongan XU