Abstract: A microelectronic device including a first nanosheet transistors adjacent to a second nanosheet transistor. The first nanosheet transistor includes a plurality of first nanosheets, and the second nanosheet transistor includes a plurality of second nanosheets. A source/drain located between the first nanosheet transistor and second nanosheet transistor. A first gate wraps around the plurality of first nanosheets. A second gate wraps around the plurality of second nanosheets. A first upper spacer located adjacent to the first gate, where the first upper spacer is in contact with at least three sides of the first gate. A second upper spacer located adjacent to the second gate, where the second upper spacer is in contact with at least three sides of the second gate. A backside interconnect connected to the source/drain, where the backside interconnect is in contact with the first upper spacer and the second upper spacer.

Abstract: According to an embodiment of the present invention, a semiconductor device includes an underlying substrate layer. A backside interlayer dielectric (BILD) layer in direct contact with a backside of the underlying substrate layer. A width of the BILD is greater than a width of the underlying substrate layer. A backside source/drain contact formed through the BILD layer. A width of the backside source/drain contact is identical to the width of the BILD layer.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.

Abstract: A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and between the first and second source-drain regions. Also included are a front side wiring network, having a plurality of front side wires, on a front side of the field effect transistor; a front side conductive path electrically interconnecting one of the front side wires with the first source-drain region; a back side power rail, on a back side of the FET; and a back side contact electrically interconnecting the back side power rail with the second source-drain region. A dielectric liner and back side dielectric fill are on a back side of the gate adjacent the back side contact, and they electrically confine the back side contact in a cross-gate direction.

Abstract: A microelectronic interconnect structure that includes, a first metal line located at a first level, a second metal line located at a second level, wherein the first level and the second level are different levels, and a connecting via that connects the first metal line to the second metal line, wherein the connecting via includes a horizontal section and trench extenders, wherein the horizontal section is located on top of the first metal line, and the trench extenders extend down sidewalls of the first metal line.

Abstract: A microelectronic structure, comprising a nanosheet field-effect-transistor (FET) is provided that includes a source/drain and a backside contact connected to a backside surface of the source/drain. The backside contact has a first section having a first width as measured perpendicular to a gate direction. The backside contact also has a second section having a second width as measured perpendicular to the gate direction. The first width is smaller than the second width. A vertical dielectric liner is provided that includes a plurality of vertical segments. Each of the vertical segments are located adjacent to a sidewall of a first section of the backside contact. A backside interlayer dielectric layer is located adjacent to the vertical dielectric liner. The backside contact is in contact with the backside interlayer dielectric layer between the two vertical segments of the plurality vertical segments of the dielectric liner.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Abstract: A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

Abstract: A semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first inner spacer and a second inner spacer disposed on a silicon layer, a third inner spacer disposed on the first inner spacer, a fourth inner spacer disposed on the second inner spacer, a gate region disposed on the silicon layer, and a source/drain region disposed on a backside source/drain contact, where an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and where the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level on top of a supporting structure and the metal level includes a first metal line of a first type and a second metal line of a second type, where the metal line of the first type has a first section and a second section on top of the first section, the first section includes a first type of ruthenium having a first impurity level and the second section includes a second type of ruthenium having a second impurity level, the first impurity level is lower than the second impurity level, and where the second metal line of the second type includes the first type of ruthenium and is devoid of the second type of ruthenium. A method of forming the same is also provided.

Abstract: A semiconductor IC structure includes a dielectric contact liner between an upper S/D region backside contact and a lower S/D region. As a result of the dielectric contact liner, the overlap between the upper transistor and the lower transistor may be increased, which may lead to further device scaling. To achieve these benefits, material that later forms the dielectric contact liner is deposited within an associated upper S/D region backside contact opening and has etch selectivity that may result in a later self-aligned reformation of the backside contact opening with reduced risk of that opening extending into the neighboring lower S/D region. The ability to self-align the formation of the backside contact opening may allow for the placement of such opening to be relatively closer to lower S/D region. The dielectric contact liner material may remain between and adequately electrically isolate the backside contact and the lower S/D region.

Abstract: Embodiments of the present disclosure include a semiconductor structure having a transistor adjacent to a shallow trench isolation (STI) region. The STI region includes a first liner, a second liner, and fill material. The second liner is pinched off in a portion of the STI region. A backside contact is coupled to the transistor, the first liner, and the second liner.

Abstract: A semiconductor device includes a top transistor stacked over a bottom transistor, a backside contact connected to a source/drain region of the bottom transistor, and a via connecting a source/drain region of the top transistor to a backside power rail (BPR). The backside contact has a T-shape profile both in a first direction and in a second direction, which is orthogonal to the first direction.

Abstract: A semiconductor device is provided including NS-FETs in which the active area module, the shallow trench isolation module and the gate module are eliminated from the processing of the semiconductor device. The elimination of these modules makes the overall process easier and aids in reducing the cost of manufacturing the semiconductor device.

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the first metal line being vertically aligned with sidewalls of the upper portion of the first metal line; a second metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the second metal line being vertically aligned with sidewalls of the upper portion of the second metal line; a dielectric liner lining sidewalls of the lower and upper portions of the first metal line and sidewalls of the lower and upper portions of the second metal line; and an isolation layer between the first and second metal lines, the isolation layer including an airgap. A method of forming the same is also provided.

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Abstract: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.