Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A remote network server includes primary and secondary routers, each of which include means for emulating a number of different modem types, and for operating in accordance with a number of different communication protocols. Incoming calls are directed at the primary router, but are routed through the secondary router if either the type of modem making a call cannot be emulated in the primary router or if the primary router cannot operate with the protocol used by this calling modem.

Abstract: A communications adapter card provides an interface for a TI or E1 transmission line and a signal processing circuit which can be programmed to process receive and transmit data in either an ISDN or an ATM format. Preferably, two such interfaces and two such signal processing circuits are provided on the card, so that a single adapter card can be used for attachment to both an ISDN network and to an ATM network. Each signal processing circuit includes a pair of DSPs, each of which has a two port buffer extending to a parallel bus. All such DSPs are connected to a data bus. The DSPs in each signal processing circuit execute programs to operate in either an ATM mode or an ISDN mode.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A pulse code modulation (PCM) unit is connected to a bus in a computer system. Also, connected to the bus is a processor and memory. The PCM unit is connected to transmit and receive telephone lines. The PCM unit reads uncompressed PCM data from the memory over the bus and compresses the PCM data for transmission over the telephone line in a cycle steal operation, wherein the bus is not being used by the processor. The PCM receives compressed PCM data from the receive telephone line, decompresses it, and writes the decompressed PCM data to the memory in a cycle steal operation. In addition, selectivity of either .mu.-Law or A-Law conversion, selectivity of even bit inversion for A-Law conversion, and selectivity between the compressed/decompressed PCM data or raw data is provided on a per channel basis. Selectable linear gain is also provided.

Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a-set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

Abstract: A digital signal processing system includes a first and second memory coupled to first and second register banks respectively. The system further includes first and second multipliers coupled to the first and second register banks for producing first and second product outputs respectively. The system also includes an arithmetic logic unit having first, second and third inputs and an output. The first input is coupled to the first product output and the second and third inputs are selectively coupled to either of the second product output and the first and second register means. The arithmetic logic unit output is coupled to the first and second register banks for accumulating the sample values in the first and second register banks. The system further includes Instruction control for storing a plurality of instruction op codes and controlling the system to compute the sample values by performing simplex operations during each cycle of a plurality of operating cycles of a digital signal processing procedure.