Patents by Inventor John Cocke

John Cocke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5805832
    Abstract: The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The source text is first transduced into one or more intermediate structural representations. From these intermediate source structures a set of intermediate target-structure hypotheses is generated. These hypotheses are scored by two different models: a language model which assigns a probability or score to an intermediate target structure, and a translation model which assigns a probability or score to the event that an intermediate target structure is translated into an intermediate source structure. Scores from the translation model and language model are combined into a combined score for each intermediate target-structure hypothesis.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 8, 1998
    Assignee: International Business Machines Corporation
    Inventors: Peter Fitzhugh Brown, John Cocke, Stephen Andrew Della Pietra, Vincent Joseph Della Pietra, Frederick Jelinek, Jennifer Ceil Lai, Robert Leroy Mercer
  • Patent number: 5768603
    Abstract: The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The source text is first transduced into one or more intermediate structural representations. From these intermediate source structures a set of intermediate target-structure hypotheses is generated. These hypotheses are scored by two different models: a language model which assigns a probability or score to an intermediate target structure, and a translation model which assigns a probability or score to the event that an intermediate target structure is translated into an intermediate source structure. Scores from the translation model and language model are combined into a combined score for each intermediate target-structure hypothesis.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Peter Fitzhugh Brown, John Cocke, Stephen Andrew Della Pietra, Vincent Joseph Della Pietra, Frederick Jelinek, Jennifer Ceil Lai, Robert Leroy Mercer
  • Patent number: 5477451
    Abstract: The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The source text is first transduced into one or more intermediate structural representations. From these intermediate source structures a set of intermediate target-structure hypotheses is generated. These hypotheses are scored by two different models: a language model which assigns a probability or score to an intermediate target structure, and a translation model which assigns a probability or score to the event that an intermediate target structure is translated into an intermediate source structure. Scores from the translation model and language model are combined into a combined score for each intermediate target-structure hypothesis.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: December 19, 1995
    Assignee: International Business Machines Corp.
    Inventors: Peter F. Brown, John Cocke, Stephen A. Della Pietra, Vincent J. Della Pietra, Frederick Jelinek, Jennifer C. Lai, Robert L. Mercer
  • Patent number: 4992938
    Abstract: A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.
    Type: Grant
    Filed: April 23, 1990
    Date of Patent: February 12, 1991
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Gregory F. Grohoski, Vojin G. Oklobdzija
  • Patent number: 4969118
    Abstract: A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: November 6, 1990
    Assignee: International Business Machines Corporation
    Inventors: Robert K. Montoye, John Cocke
  • Patent number: 4937736
    Abstract: A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: June 26, 1990
    Assignee: International Business Machines Corporation
    Inventors: Albert Chang, John Cocke, Mark F. Mergen, Richard R. Oehler
  • Patent number: 4802091
    Abstract: A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law of addition. To achieve this, the requisite optimization of an object program or program segment, the following discrete steps must be performed after the strongly connected regions, USE and DEF chains have all been identified:1. Find the region constants and induction variables;2. Identify all of the essential computations;3. Write every essential computation as a sum of products;4. Exploit the use and DEF functions to substitute the definition of each operand R in an essential computation, if there is a unique computation of R in the strongly connected region and the defining operation is +, -, .times., or copy;5. Fix displacements;6.
    Type: Grant
    Filed: October 31, 1986
    Date of Patent: January 31, 1989
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Peter W. Markstein
  • Patent number: 4719568
    Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement within the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory.The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Modification of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: January 12, 1988
    Assignee: International Business Machines Corporation
    Inventors: Francis P. Carrubba, John Cocke, Norman H. Kreitzer
  • Patent number: 4710868
    Abstract: A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.
    Type: Grant
    Filed: June 29, 1984
    Date of Patent: December 1, 1987
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Brent T. Hailpern
  • Patent number: 4656583
    Abstract: A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises:Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the "kill set" for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and "kill set" information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.
    Type: Grant
    Filed: August 13, 1984
    Date of Patent: April 7, 1987
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Auslander, John Cocke, Peter W. Markstein
  • Patent number: 4642765
    Abstract: A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss of program accuracy. The method comprises placing a range check trap instruction into the header node of the SCR provided there is only one conditional exit from the SCR, modifying the conditional exit test based on the value of the induction variable v, and inserting a new check at the loop exit point(s) to insure that the induction variable has reached the value it would have obtained in the original (unmodified) program.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: February 10, 1987
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Peter W. Markstein, Victoria I. Markstein
  • Patent number: 4638426
    Abstract: A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step.
    Type: Grant
    Filed: September 19, 1983
    Date of Patent: January 20, 1987
    Assignee: International Business Machines Corporation
    Inventors: Albert Chang, John Cocke, Mark F. Mergen, George Radin
  • Patent number: 4589087
    Abstract: A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: May 13, 1986
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Auslander, John Cocke, Hsieh T. Hao, Peter W. Markstein, George Radin
  • Patent number: 4589065
    Abstract: A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: May 13, 1986
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Auslander, John Cocke, Hsieh T. Hao, Peter W. Markstein, George Radin
  • Patent number: 4587579
    Abstract: An information reading/writing head is positioned to follow data tracks that are formed concentrically on a magnetic recording disk. A set of spiral radial position-indicating markings if formed which can be detected on the disk optically, or capacitively. The position of the head is determined by sensing the spiral markings. The reference for the phase detection is detected by sensing radial indicia on the disk periphery or spiral markings of servo data with a different pitch and frequency from the position-indicating spiral markings. A servo control system operated by the above disk, reads the radial position-indicating spiral pattern and the reference pattern on the disk and compares the relative phases of the two to compute the track position of the head. A set of phase-locked loops with subsequent phase comparators is used to decode the servo data.
    Type: Grant
    Filed: December 30, 1982
    Date of Patent: May 6, 1986
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Thomas H. DiStefano
  • Patent number: 4564944
    Abstract: A method and an apparatus are disclosed for converting error syndromes of an error-correcting code to pointers which identify the positions of the erroneous bits. Each syndrome is converted by a plurality of hashing functions into a plurality of hash words, which in turn are used to address a plurality of read-only stores. The outputs of the read-only stores are logically combined to obtain the respective error pointer. A preferred embodiment uses three hashing functions (41, 43, 45) and three read-only stores (53, 55, 57) and combines their outputs by an Exclusive-Or function (59). The storage capacity and the processing time required for syndrome-to-error pointer conversion are reduced by the disclosed scheme.
    Type: Grant
    Filed: December 30, 1983
    Date of Patent: January 14, 1986
    Assignee: International Business Machines Corporation
    Inventors: Richard F. Arnold, John Cocke, Don Coppersmith, Adrian E. Seigler, Gary E. Strait
  • Patent number: 4306286
    Abstract: A hardware logic simulation machine comprised of an array of specially designed parallel processors, with there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory. Logic values simulated by one processor are communicated to other processors by a switching mechanism controlled by a controller. If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
    Type: Grant
    Filed: June 29, 1979
    Date of Patent: December 15, 1981
    Assignee: International Business Machines Corporation
    Inventors: John Cocke, Richard L. Malm, John J. Shedletsky
  • Patent number: 4291406
    Abstract: A sequential decoder for error correction on burst and random noise channels using convolutionally encoded data. The decoder interacts with a deinterleaver which time demultiplexes data from a data channel from its time multiplexed form into a predetermined transformed order. The decoder includes a memory for storing a table of likelihood values which are derived from known error statistics about the data channel such as the probabilities of random errors and burst errors, burst error severity and burst duration. The decoder removes an encoded subblock of data from the deinterleaver and enters it into a replica of the convolutional encoder which calculates a syndrome bit from a combination of the presently received subblock together with a given number of previous subblocks. The syndrome bit indicates if the current assumption of the path through the convolutional tree is correct.
    Type: Grant
    Filed: August 6, 1979
    Date of Patent: September 22, 1981
    Assignee: International Business Machines Corporation
    Inventors: Lalit R. Bahl, John Cocke, Clifton D. Cullum, Jr., Joachim Hagenauer
  • Patent number: RE37305
    Abstract: A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventors: Albert Chang, John Cocke, Mark F. Mergen, George Radin