Patents by Inventor John CODDINGTON

John CODDINGTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847394
    Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: December 19, 2023
    Assignee: Arteris, Inc.
    Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
  • Publication number: 20230388216
    Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Applicant: ARTERIS, INC.
    Inventors: John CODDINGTON, Boon CHUAN
  • Patent number: 11831557
    Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: November 28, 2023
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
  • Patent number: 11805080
    Abstract: A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
    Type: Grant
    Filed: July 16, 2022
    Date of Patent: October 31, 2023
    Assignee: ARTERIS, INC.
    Inventor: John Coddington
  • Patent number: 11757798
    Abstract: A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 12, 2023
    Assignee: ARTERIS, INC.
    Inventor: John Coddington
  • Patent number: 11729088
    Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: August 15, 2023
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Boon Chuan
  • Publication number: 20230132724
    Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
    Type: Application
    Filed: September 5, 2022
    Publication date: May 4, 2023
    Applicant: ARTERIS, INC.
    Inventors: Syed Ijlal Ali SHAH, John CODDINGTON, Benoit de LESCURE
  • Publication number: 20220353205
    Abstract: A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
    Type: Application
    Filed: July 16, 2022
    Publication date: November 3, 2022
    Applicant: ARTERIS, INC.
    Inventor: John CODDINGTON
  • Publication number: 20220303224
    Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Applicant: ARTERIS, INC.
    Inventors: John CODDINGTON, Benoit de LESCURE, Syed IJLAL ALI SHAH, Sanjay DESPANDE
  • Patent number: 11436185
    Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 6, 2022
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Publication number: 20220210096
    Abstract: A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: ARTERIS, INC.
    Inventor: John CODDINGTON
  • Publication number: 20220210046
    Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: ARTERIS, INC.
    Inventors: John CODDINGTON, Boon CHUAN
  • Publication number: 20220210085
    Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: ARTERIS, INC.
    Inventors: John CODDINGTON, Benoit de LESCURE, Syed IJLAL ALI SHAH, Sanjay DESPANDE
  • Patent number: 11368402
    Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: June 21, 2022
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
  • Publication number: 20220180034
    Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 9, 2022
    Applicant: Arteris, Inc.
    Inventors: John CODDINGTON, Sylvain MELICIANI, Frederic GREUS, Xavier Van RUYMBEKE
  • Patent number: 11210445
    Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: December 28, 2021
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
  • Publication number: 20210149836
    Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 20, 2021
    Applicant: ARTERIS, INC.
    Inventors: Syed Ijlal SHAH, John CODDINGTON, Benoit de LESCURE