Patents by Inventor John CODDINGTON
John CODDINGTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11847394Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: GrantFiled: December 2, 2021Date of Patent: December 19, 2023Assignee: Arteris, Inc.Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
-
Publication number: 20230388216Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.Type: ApplicationFiled: August 14, 2023Publication date: November 30, 2023Applicant: ARTERIS, INC.Inventors: John CODDINGTON, Boon CHUAN
-
Patent number: 11831557Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.Type: GrantFiled: June 8, 2022Date of Patent: November 28, 2023Assignee: ARTERIS, INC.Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
-
Patent number: 11805080Abstract: A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.Type: GrantFiled: July 16, 2022Date of Patent: October 31, 2023Assignee: ARTERIS, INC.Inventor: John Coddington
-
Patent number: 11757798Abstract: A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.Type: GrantFiled: December 28, 2020Date of Patent: September 12, 2023Assignee: ARTERIS, INC.Inventor: John Coddington
-
Patent number: 11729088Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.Type: GrantFiled: December 30, 2020Date of Patent: August 15, 2023Assignee: ARTERIS, INC.Inventors: John Coddington, Boon Chuan
-
Publication number: 20230132724Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.Type: ApplicationFiled: September 5, 2022Publication date: May 4, 2023Applicant: ARTERIS, INC.Inventors: Syed Ijlal Ali SHAH, John CODDINGTON, Benoit de LESCURE
-
Publication number: 20220353205Abstract: A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.Type: ApplicationFiled: July 16, 2022Publication date: November 3, 2022Applicant: ARTERIS, INC.Inventor: John CODDINGTON
-
Publication number: 20220303224Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.Type: ApplicationFiled: June 8, 2022Publication date: September 22, 2022Applicant: ARTERIS, INC.Inventors: John CODDINGTON, Benoit de LESCURE, Syed IJLAL ALI SHAH, Sanjay DESPANDE
-
Patent number: 11436185Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.Type: GrantFiled: November 15, 2019Date of Patent: September 6, 2022Assignee: ARTERIS, INC.Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
-
Publication number: 20220210096Abstract: A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Applicant: ARTERIS, INC.Inventor: John CODDINGTON
-
Publication number: 20220210046Abstract: A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Applicant: ARTERIS, INC.Inventors: John CODDINGTON, Boon CHUAN
-
Publication number: 20220210085Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: ARTERIS, INC.Inventors: John CODDINGTON, Benoit de LESCURE, Syed IJLAL ALI SHAH, Sanjay DESPANDE
-
Patent number: 11368402Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.Type: GrantFiled: December 26, 2020Date of Patent: June 21, 2022Assignee: ARTERIS, INC.Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
-
Publication number: 20220180034Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: ApplicationFiled: December 2, 2021Publication date: June 9, 2022Applicant: Arteris, Inc.Inventors: John CODDINGTON, Sylvain MELICIANI, Frederic GREUS, Xavier Van RUYMBEKE
-
Patent number: 11210445Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.Type: GrantFiled: December 9, 2020Date of Patent: December 28, 2021Assignee: ARTERIS, INC.Inventors: John Coddington, Sylvain Meliciani, Frederic Greus, Xavier Van Ruymbeke
-
Publication number: 20210149836Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Applicant: ARTERIS, INC.Inventors: Syed Ijlal SHAH, John CODDINGTON, Benoit de LESCURE