Patents by Inventor John Cohn
John Cohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11682047Abstract: A method, computer system, and computer program product for cognitive elevator advertisements are provided. The embodiment may include identifying one or more passengers utilizing real-time sensor data. The embodiment may also include determining a preference value of each identified passenger for a plurality of product categories based on a plurality of data related to past purchase histories or purchasing patterns received from a plurality of databases simultaneously or almost simultaneously. The embodiment may further include computing corrected passenger preference values for the plurality of product categories based on unprejudiced preference values of the passengers multiplied by the preference values assigned to each product category. The embodiment may also include determining one or more targeted advertisements for one or more targeted passengers based on each computed passenger preference values.Type: GrantFiled: August 28, 2018Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Anthony J. P. Behan, Ninad Sathaye, John Cohn, Rick A. Hamilton, II
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Publication number: 20200074508Abstract: A method, computer system, and computer program product for cognitive elevator advertisements are provided. The embodiment may include identifying one or more passengers utilizing real-time sensor data. The embodiment may also include determining a preference value of each identified passenger for a plurality of product categories based on a plurality of data related to past purchase histories or purchasing patterns received from a plurality of databases simultaneously or almost simultaneously. The embodiment may further include computing corrected passenger preference values for the plurality of product categories based on unprejudiced preference values of the passengers multiplied by the preference values assigned to each product category. The embodiment may also include determining one or more targeted advertisements for one or more targeted passengers based on each computed passenger preference values.Type: ApplicationFiled: August 28, 2018Publication date: March 5, 2020Inventors: Anthony J.P. Behan, Ninad Sathaye, John Cohn, Rick A. Hamilton, II
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Publication number: 20080074147Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.Type: ApplicationFiled: December 7, 2007Publication date: March 27, 2008Inventors: John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Thomas Lepsic, Jagannathan Narasimhan, Scott Tetreault, Sebastian Ventrone
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Publication number: 20080018872Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.Type: ApplicationFiled: October 1, 2007Publication date: January 24, 2008Inventors: Robert Allen, John Cohn, Scott Gould, Peter Habitz, Juergen Koehl, Gustavo Tellez, Ivan Wemple, Paul Zuchowski
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Publication number: 20080017857Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: ApplicationFiled: September 24, 2007Publication date: January 24, 2008Inventors: James Adkisson, Greg Bazan, John Cohn, Matthew Grady, Thomas Sopchak, David Vallett
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Publication number: 20070160920Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: ApplicationFiled: March 19, 2007Publication date: July 12, 2007Inventors: James Adkisson, Greg Bazan, John Cohn, Matthew Grady, Thomas Sopchak, David Vallett
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Publication number: 20070143728Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.Type: ApplicationFiled: February 16, 2007Publication date: June 21, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Cohn, Jason Hibbeler, Anthony Stamper, Jed Rankin
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Publication number: 20070136714Abstract: Embodiments herein present a method, service, computer program product, etc. or performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.Type: ApplicationFiled: December 8, 2005Publication date: June 14, 2007Inventors: John Cohn, Jason Hibbeler, Gustavo Tellez
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Publication number: 20070108964Abstract: Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.Type: ApplicationFiled: May 10, 2006Publication date: May 17, 2007Inventors: John Cohn, Leah Pastel, Thomas Sopchak, David Vallett
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Publication number: 20060265684Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Markus Buehler, John Cohn, David Hathaway, Jason Hibbeler, Juergen Koehl
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Publication number: 20060225023Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: ApplicationFiled: April 4, 2005Publication date: October 5, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Greg Bazan, John Cohn, Matthew Grady, Thomas Sopchak, David Vallett
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Publication number: 20060195809Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Cohn, Jason Hibbeler, Anthony Stamper, Jed Rankin
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Publication number: 20060190744Abstract: An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.Type: ApplicationFiled: February 22, 2005Publication date: August 24, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rafael Blanco, John Cohn, Kenneth Goodnow, Douglas Stout, Sebastian Ventrone
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Publication number: 20060170104Abstract: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.Type: ApplicationFiled: March 28, 2006Publication date: August 3, 2006Applicant: International Business Machines CorporationInventors: John Cohn, Leah Pastel, Thomas Sopchak, David Vallett
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Publication number: 20060066342Abstract: Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.Type: ApplicationFiled: November 16, 2005Publication date: March 30, 2006Inventors: John Cohn, Leah Pastel, Thomas Sopchak, David Vallett
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Publication number: 20060038602Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.Type: ApplicationFiled: October 21, 2005Publication date: February 23, 2006Inventors: Anthony Bonaccio, John Cohn, Alvar Dean, Amir Farrahi, David Hathaway, Sebastian Ventrone
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Publication number: 20060036977Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.Type: ApplicationFiled: August 12, 2004Publication date: February 16, 2006Inventors: John Cohn, James Culp, Ulrich Finkler, Fook-Luen Heng, Mark Lavin, Jin Lee, Lars Liebmann, Gregory Northrop, Nakgeuon Seong, Rama Singh, Leon Stok, Pieter Woltgens
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Publication number: 20060036975Abstract: A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Greg Bazan, John Cohn, Francis Gravel, Leendert Huisman, Phillip Nigh, Leah Pastel, Kenneth Rowe, Thomas Sopchak, David Sweenor
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Publication number: 20060036976Abstract: A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and one or more corresponding wire segments adjacent to the continuous wire, the continuous wire separated from the one or more corresponding wire segments by a space; and connecting the continuous wire and the one or more wire segments to circuit elements of a defect monitor scan chain, the circuit elements previously inserted into the integrated circuit design.Type: ApplicationFiled: August 13, 2004Publication date: February 16, 2006Applicant: International Business Machines CorporationInventors: John Cohn, Leah Pastel
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Publication number: 20060022693Abstract: A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.Type: ApplicationFiled: July 27, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Greg Bazan, John Cohn, Matthew Grady, Phillip Nigh, Leah Pastel, Thomas Sopchak