Patents by Inventor John Contreras

John Contreras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145424
    Abstract: A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.
    Type: Application
    Filed: July 19, 2023
    Publication date: May 2, 2024
    Inventors: John Contreras, Nagesh Vodrahalli, Md. Sayed Mobin
  • Patent number: 11961542
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240040688
    Abstract: A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Masahiro Kishimoto, John Contreras, Kazuhiro Nagaoka, Satoshi Nakamura
  • Patent number: 11874182
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: January 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240005957
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 4, 2024
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240003750
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 4, 2024
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Patent number: 11818834
    Abstract: A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Masahiro Kishimoto, John Contreras, Kazuhiro Nagaoka, Satoshi Nakamura
  • Publication number: 20220418092
    Abstract: A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Masahiro Kishimoto, John Contreras, Kazuhiro Nagaoka, Satoshi Nakamura
  • Patent number: 11276424
    Abstract: Disclosed herein is a data storage device comprising a slider comprising an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both (a) couple a slider bias voltage to a body of the slider to control a potential of the slider, and (b) provide a signal to the embedded contact sensor. The slider may also include a shunt circuit for mitigating radio-frequency interference by shunting it to ground. The slider may include a write element, which may include a write-field enhancement structure. The slider may include a read element for reading from a recording media.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Publication number: 20210327462
    Abstract: Disclosed herein is a data storage device comprising a slider comprising an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both (a) couple a slider bias voltage to a body of the slider to control a potential of the slider, and (b) provide a signal to the embedded contact sensor. The slider may also include a shunt circuit for mitigating radio-frequency interference by shunting it to ground. The slider may include a write element, which may include a write-field enhancement structure. The slider may include a read element for reading from a recording media.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Patent number: 11087784
    Abstract: Disclosed herein is a data storage device comprising a recording media, a slider comprising a write head having a write-field enhancement structure for recording data to the recording media, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and carry a bias current for the write-field enhancement structure. Also disclosed herein is a data storage device comprising a slider with an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and provide a signal to the embedded contact sensor.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Patent number: 10891973
    Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 12, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Publication number: 20200349969
    Abstract: Disclosed herein is a data storage device comprising a recording media, a slider comprising a write head having a write-field enhancement structure for recording data to the recording media, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and carry a bias current for the write-field enhancement structure. Also disclosed herein is a data storage device comprising a slider with an embedded contact sensor, an electronics module, and a plurality of lines disposed between and coupled to the slider and the electronics module, wherein at least one line of the plurality of lines is configured to both couple a bias voltage to a body of the slider, and provide a signal to the embedded contact sensor.
    Type: Application
    Filed: March 30, 2020
    Publication date: November 5, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: John CONTRERAS, Yunfei DING, Kuok San HO, Ian Robson MCFADYEN, Joey Martin POSS
  • Publication number: 20200211584
    Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: John CONTRERAS, Yunfei DING, Kuok San HO, Ian Robson MCFADYEN, Joey Martin POSS
  • Patent number: 10629229
    Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Publication number: 20190362744
    Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
    Type: Application
    Filed: August 11, 2019
    Publication date: November 28, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: John CONTRERAS, Yunfei DING, Kuok San HO, Ian Robson MCFADYEN, Joey Martin POSS
  • Patent number: 10424323
    Abstract: Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 24, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Yunfei Ding, Kuok San Ho, Ian Robson McFadyen, Joey Martin Poss
  • Patent number: 10411670
    Abstract: Disclosed herein are printed circuit boards with at least one signal trace situated over or under a reference plane. The reference plane includes a broadband common-mode filter that comprises looping and parallel structures etched into the reference plane. The looping structure includes an even number of side arms, and the parallel structure comprises an even number of interior arms, wherein each of the side arms extends toward the parallel structure, and each of the interior arms extends toward the looping structure. The at least one signal trace is substantially parallel to the side arms and to the interior arms, and is situated between a first half of the even number of side arms and a second half of the even number of side arms and between a first half of the even number of interior arms and a second half of the even number of interior arms.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, Albert Wallash, John Contreras
  • Patent number: 10283150
    Abstract: Disclosed herein are suspension assembly structures for data storage devices that include physical or virtual crossovers of the pairs of differential signal traces to improve immunity to crosstalk and other interference. In an embodiment, the suspension assembly structure comprises a first trace for carrying a first component of a current to a differential transducer on a slider, a second trace for carrying a second component of the current to the differential transducer on the slider, and third and fourth traces for providing a differential write current to a writer of the data storage device, wherein the first trace physically crosses over the second trace at a first distance from a tail of the suspension assembly structure.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 7, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Rehan Zakai, Albert Wallash, Tzong-Shii Pan
  • Patent number: 10285259
    Abstract: Disclosed herein are printed circuit boards with embedded solenoid filters through which signal traces pass to filter unwanted noise and electromagnetic interference. A printed circuit board comprises a least three layers, a solenoid embedded within the at least three layers, and at least one trace extending through the solenoid. The insertion loss characteristics of the solenoid filter can be tuned by modifying the number of turns in the solenoid(s) and the width of the solenoid(s). The solenoid filter may comprise multiple solenoids connected in series, with adjacent solenoids having opposite wind directions. Surface components may be included on the board to tune the insertion loss further.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 7, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Albert Wallash, John Contreras, Ronald G. Parkinen, Xinzhi Xing, Hui He