Abstract: A peripheral controller device (14) controlling at least a first peripheral device (16) attached thereto, the controller device including a programmable and selectable buffer memory for utilization with a first type and a second type of write instruction for writing data to first type (24) and a second type (26), respectively, of memory in the peripheral device (16). The peripheral controller device includes an n deep buffer memory (36), where n is an integer greater than one, for buffering the write instructions. A user may programmably indicate whether only the first type of write instruction is to be buffered or both types of instructions are to be buffered. Responsive to such programming, write instructions are examined to determine if they are of the first type or the second type. Depending on the programming, write instructions of the second type are routed to the buffer or are routed by bypassing the buffer memory.

Abstract: A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.

Abstract: An apparatus for detecting and recording the time and frequency of occurrence of events at a predetermined surveillance site includes a sensor providing successive output signals corresponding to successive detections of an event occurrence at the surveillance site. The output signals from the sensor are input to a central processing unit operating a control program stored in a memory which stores in the memory the date, time and number of occurrences of events at the surveillance site. The apparatus also includes a keyboard for inputting start date and start time information and for initiating the operation of sensing of events and the recall of stored date, time and event occurrence number information for display on a digital display mounted on the apparatus. All of the operative components of the apparatus are powered by a d.c. electric power source and are contained in a waterproof housing mountable at a predetermined surveillance site.