Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

Abstract: The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

Abstract: The present invention provides a way of placing a physical layer device into a standby mode. After a link is established between multiple devices, a determination is made whether the device has data to transmit or whether a standby request was received from a link partner. If a standby request was received or the device has no data to transmit, standby mode is entered. In standby mode, unneeded circuitry is powered down. A transmitter in a channel and a receive path in a separate channel remain powered. While operating in standby mode, the PHY layer continuously transmits a standby code on the one or more channels that are not powered down. Standby mode is discontinued when a transceiver has data to transmit or when energy is detected on the powered down channels. Standby mode is also discontinued when no standby code is received, indicating a disconnect between devices.

Abstract: Aspects of a method and system for interference cancellation substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. In this regard, a receiver may be operable to receive a differential signal via a differential channel, and to sense a common mode signal on the differential channel. A frequency range in which interference is present in the common mode signal may be determined. The differential signal and the common mode signal may be filtered to attenuate frequencies outside the determined frequency range. A phase and/or amplitude of the filtered common mode signal may be adjusted based on the filtered differential signal and the adjusted and filtered common mode signal may be subtracted from the received differential signal. The common mode signal may be sensed via a pair of resistors coupled to the differential channel.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal, By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: A multi-port transceiver includes a transmitter and receiver for each port. The invention is a test method and apparatus for testing individual components in the transmit and receive paths. Specifically, the invention includes a method of testing the full range of a programmable gain amplifier (PGA) and an analog to digital converter (ADC) in the receive path of each port. This is accomplished by connecting the transmitter of one port directly to the receiver of a second port, and varying the amplitude of the transmitter over a range of gain settings of the PGA while examining if the dynamic range of the receiver has been exceeded.

Abstract: A system and method are disclosed that provide for compatibility between different generations of transceivers, such as Gigabit Ethernet transceivers. According to the invention, a novel transceiver is provided that includes a physical layer entity (PHY) comprising a physical coding sublayer (PCS) and a physical medium attachment (PMA) sublayer. In one embodiment, the PHY is designed to switch the PCS encoding/decoding scheme to a legacy-based encoding/decoding scheme in a situation where it is determined that the remote transceiver in communication with the novel transceiver is transmitting data according to a legacy-based scheme.

Abstract: A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract: A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals. A PCS receiver encoder generator generates the encoding parameters.

Abstract: A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase.