Patents by Inventor John Cruz
John Cruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949589Abstract: Network traffic flows can be processed by routers, switches, or service nodes. Service nodes may be ASICs that can provide the functionality of a switch or a router. Service nodes can be configured in a circular replication chain, thereby providing benefits such as high reliability. The service nodes can implement methods that include receiving a first packet that includes a source address in a source address field and that includes a destination address in a destination address field, routing the first packet to a selected service node that is in a circular replication chain that includes a plurality of service nodes that have local flow tables and are configured for chain replication of the local flow tables, producing a second packet by using a matching flow table entry of the first packet to process the first packet, and sending the second packet toward a destination indicated by the destination address.Type: GrantFiled: June 30, 2021Date of Patent: April 2, 2024Assignee: Pensando Systems Inc.Inventors: Krishna Doddapaneni, Sarat Kamisetty, Balakrishnan Raman, Chandrasekaran Swaminathan, Maruthi Ram Namburu, Vijay Sampath, Akshay Nadahalli, Pirabhu Raman, John Cruz
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Publication number: 20240056348Abstract: A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.Type: ApplicationFiled: October 26, 2023Publication date: February 15, 2024Applicant: Barefoot Networks, Inc.Inventors: Chaitanya KODEBOYINA, John CRUZ, Steven LICKING, Michael E. ATTIG
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Publication number: 20240017248Abstract: A method of immobilizing a metal catalyst in a porous support includes additively forming a precursor structure on a substrate from a metal catalyst and at least one of a metal oxide or a metal cluster compound; exposing the precursor structure to a vapor of an organic linker; and reacting the at least one of the metal oxide or the metal cluster compound in the precursor structure with the organic linker to form a porous support that immobilizes the metal catalyst.Type: ApplicationFiled: July 13, 2022Publication date: January 18, 2024Applicant: Baker Hughes Oilfield Operations LLCInventors: Alexander John Cruz, Navin Sakthivel, Jayesh Jain, Michelangelo Bellacci
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Patent number: 11876696Abstract: Network appliances can use packet processing pipeline circuits to implement network rules for processing network packet flows by configuring the pipeline's processing stages to execute specific policies for specific network packets in accordance with the network rules. Trace reports that indicate network rules implemented at specific processing stages can be more informative than those indicating policies implemented by the processing stages. A method implemented by a network appliance can store network rules for processing network flows by the processing stages of a packet processing pipeline circuit. The method can produce a trace report in response to receiving a trace directive for one of the network flows wherein one of the processing stages has applied a network rule to a network packet in one of the network flows. The trace report can indicate the network rule in association with the processing stage and the network flow.Type: GrantFiled: August 31, 2021Date of Patent: January 16, 2024Assignee: PENSANDO SYSTEMS INC.Inventors: Vijay Srinivasan, Sarat Kamisetty, Krishna Doddapaneni, John Cruz, Loganathan Nallusamy
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Publication number: 20230311213Abstract: A method of manufacturing a nanoporous structure on a substrate includes: additively forming a precursor structure from at least one of a metal oxide or a metal cluster compound on a substrate; exposing the precursor structure to a vapor of an organic linker; and reacting the at least one of the metal oxide or the metal cluster compound in the precursor structure with the organic linker to form the nanoporous structure comprising a metal-organic framework.Type: ApplicationFiled: March 23, 2022Publication date: October 5, 2023Applicant: Baker Hughes Oilfield Operations LLCInventors: Alexander John Cruz, Navin Sakthivel
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Publication number: 20230069844Abstract: Synchronizing the databases maintained by network appliances can support high availability or high throughput topologies, but also consumes the devices' processing resources. To address that resource consumption, the network appliance's packet processing pipeline circuits can process synchronization packets to thereby synchronize the databases. A local data structure can be in a first local state. Processing a network packet can result in changing the local data structure to a second local state. A state sync packet can include state transition data that indicates a state difference between the first local state and the second local state. The state sync packet can be sent to a peer device that is configured to process the state transition data using the peer device's packet processing pipeline circuit. The peer device's packet processing pipeline can use the state transition data to update a peer device data structure that is in the peer device.Type: ApplicationFiled: August 25, 2021Publication date: March 9, 2023Inventors: Varagur Chandrasekaran, Akshaya Nadahalli, Balakrishnan Raman, Chandrasekaran Swaminathan, John Cruz, Maruthi Ram Namburu, Pirabhu Raman, Vijay Sampath, Vipin Jain
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Publication number: 20230068914Abstract: Network appliances can use packet processing pipeline circuits to implement network rules for processing network packet flows by configuring the pipeline's processing stages to execute specific policies for specific network packets in accordance with the network rules. Trace reports that indicate network rules implemented at specific processing stages can be more informative than those indicating policies implemented by the processing stages. A method implemented by a network appliance can store network rules for processing network flows by the processing stages of a packet processing pipeline circuit. The method can produce a trace report in response to to receiving a trace directive for one of the network flows wherein one of the processing stages has applied a network rule to a network packet in one of the network flows. The trace report can indicate the network rule in association with the processing stage and the network flow.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Vijay Srinivasan, Sarat Kamisetty, Krishna Doddapaneni, John Cruz, Loganathan Nallusamy
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Publication number: 20230064845Abstract: An orchestrator can send trace directives to network appliances that indicate a network flow to trace. The network appliances can include packet processing pipelines that each include numerous processing stages. The network appliances implement network rules for processing network flows by configuring the pipeline's processing stages to execute specific policies for specific network packets in accordance with the network rules. The processing stages can also be configured to produce metadata indicating the policies implemented at each stage to process certain network packets in network flows indicated by trace directives. The metadata can be used to produce a trace report that indicates a network packet of the network flow, a first network rule that was applied to the network packet by a one of the first appliance processing stages, and the one of the first appliance processing stages that applied the first network rule to the network packet.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Vijay Srinivasan, Sarat Kamisetty, Krishna Doddapaneni, John Cruz, Loganathan Nallusamy
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Publication number: 20220377013Abstract: Network traffic flows can be processed by routers, switches, or service nodes. Service nodes may be ASICs that can provide the functionality of a switch or a router. Service nodes can be configured in a circular replication chain, thereby providing benefits such as high reliability. The service nodes can implement methods that include receiving a first packet that includes a source address in a source address field and that includes a destination address in a destination address field, routing the first packet to a selected service node that is in a circular replication chain that includes a plurality of service nodes that have local flow tables and are configured for chain replication of the local flow tables, producing a second packet by using a matching flow table entry of the first packet to process the first packet, and sending the second packet toward a destination indicated by the destination address.Type: ApplicationFiled: June 30, 2021Publication date: November 24, 2022Inventors: Krishna Doddapaneni, Sarat Kamisetty, Balakrishnan Raman, Chandrasekaran Swaminathan, Maruthi Ram Namburu, Vijay Sampath, Akshay Nadahalli, Pirabhu Raman, John Cruz
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Publication number: 20220321400Abstract: A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.Type: ApplicationFiled: April 18, 2022Publication date: October 6, 2022Inventors: Chaitanya KODEBOYINA, John CRUZ, Steven LICKING, Michael E. ATTIG
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Patent number: 11310099Abstract: A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.Type: GrantFiled: June 16, 2020Date of Patent: April 19, 2022Assignee: Barefoot Networks, Inc.Inventors: Chaitanya Kodeboyina, John Cruz, Steven Licking, Michael E. Attig
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Patent number: 10884758Abstract: Aspects of the embodiments are directed to propagating an in-band hot reset through an add-in card compliant with a peripheral component interconnect express (PCIe) protocol. A host system can transmit an in-band hot reset to the add-in card across a link compliant with the PCIe protocol. A non-transparent bridge (NTB) on the add-in card can receive the in-band hot reset and reset configuration registers on the NTB. A system management controller can poll the NTB register values to determine that the polled configuration registers are different from expected values stored on an electrically erasable programmable random access memory (EEPROM). The SMC can signal a warm reset to a peripheral component based on the determination that the polled configuration register value is different from the expected register value.Type: GrantFiled: July 1, 2017Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Georges Manuel Faure Vaquero, John Cruz Mejia, Scott M. Rider, David M. Lee
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Patent number: 10859627Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.Type: GrantFiled: June 29, 2017Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah, Michael Neve de Mevergnies, John Cruz Mejia, Amy L. Santoni
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Publication number: 20200313955Abstract: A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Inventors: Chaitanya Kodeboyina, John Cruz, Steven Licking, Michael E. ATTIG
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Patent number: 10601702Abstract: A novel method for replicating and filtering multicast packet in a physical network is provided. Upon receiving a packet, the method generates a set of metadata as ingress replication context for the received packet based on the content of the receive packet. The generated ingress replication context includes a multicast group identifier, a replication identifier, a first layer exclusion identifier, and a second layer exclusion identifier. The method performs multicast replication of the packet by identifying logical ports and/or logical domains that are to be excluded from the multicast replication based on the content of the generated ingress replication context.Type: GrantFiled: July 2, 2018Date of Patent: March 24, 2020Assignee: Barefoot Networks, Inc.Inventors: John Cruz, Chaitanya Kodeboyina
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Publication number: 20190004112Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Sorin Iacobovici, Neel Shah, Michael Neve de Mevergnies, John Cruz Mejia, Amy L. Santoni
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Publication number: 20180321948Abstract: Aspects of the embodiments are directed to propagating an in-band hot reset through an add-in card compliant with a peripheral component interconnect express (PCIe) protocol. A host system can transmit an in-band hot reset to the add-in card across a link compliant with the PCIe protocol. A non-transparent bridge (NTB) on the add-in card can receive the in-band hot reset and reset configuration registers on the NTB. A system management controller can poll the NTB register values to determine that the polled configuration registers are different from expected values stored on an electrically erasable programmable random access memory (EEPROM). The SMC can signal a warm reset to a peripheral component based on the determination that the polled configuration register value is different from the expected register value.Type: ApplicationFiled: July 1, 2017Publication date: November 8, 2018Applicant: Intel CorporationInventors: Georges Manuel Faure Vaquero, John Cruz Mejia, Scott M. Rider, David M. Lee
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Patent number: 10063407Abstract: A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.Type: GrantFiled: May 9, 2016Date of Patent: August 28, 2018Assignee: BAREFOOT NETWORKS, INC.Inventors: Chaitanya Kodeboyina, John Cruz, Steven Licking, Michael E. Attig
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Patent number: 10038624Abstract: A novel method for replicating and filtering multicast packet in a physical network is provided. Upon receiving a packet, the method generates a set of metadata as ingress replication context for the received packet based on the content of the receive packet. The generated ingress replication context includes a multicast group identifier, a replication identifier, a first layer exclusion identifier, and a second layer exclusion identifier. The method performs multicast replication of the packet by identifying logical ports and/or logical domains that are to be excluded from the multicast replication based on the content of the generated ingress replication context.Type: GrantFiled: April 5, 2016Date of Patent: July 31, 2018Assignee: BAREFOOT NETWORKS, INC.Inventors: John Cruz, Chaitanya Kodeboyina
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Patent number: 8067535Abstract: The present invention relates to the identification of gene sequences and proteins involved in vaccinia virus dominant T cell epitopes. Three vaccinia virus CD8+ T cell epitopes restricted by the most common human M.C. class I allele, HLA-A0201, were identified. Each of these epitopes is highly conserved in vaccinia and variola viruses. In addition, the induction of the T cell responses following primary vaccination with two of these epitopes is demonstrated by the kinetics of epitope specific CD8+ T cells in 3 HLA-A0201 individuals. Two vaccinia virus CD8+ T cell epitopes restricted by another common human M.C. class I allele, HLA-B7, also were identified. Both epitopes are highly conserved in vaccinia and variola viruses. This information will be useful for the design and analysis of the immunogenicity of experimental vaccinia vaccines, and for basic studies of human T cell memory.Type: GrantFiled: September 28, 2005Date of Patent: November 29, 2011Assignee: The University of MassachusettsInventors: Masanori Terajima, John Cruz, Francis A. Ennis