Abstract: A wireless communications transmitter is divided into N binary weighted communication signal processing paths including both fixed and variable gain communication signal processing chains. Specific bit sequences are used to select a combination of fixed and variable gain signal processing paths to adjust to a desired transmitter output power. Alternately, high and low power communication signal processing paths are chosen as needed with the high power communication signal processing path including an odd order harmonic notch filter.

Abstract: A wireless communications transmitter is divided into N binary weighted communication signal processing paths including both fixed and variable gain communication signal processing chains. Specific bit sequences are used to select a combination of fixed and variable gain signal processing paths to adjust to a desired transmitter output power. Alternately, high and low power communication signal processing paths are chosen as needed with the high power communication signal processing path including an odd order harmonic notch filter.

Abstract: Various configurations and arrangements of systems and methods for providing multi-carrier aggregation are described. A system in accordance with the disclosure can include a first mixer configured to receive a first signal in a first frequency band, a second mixer configured to receive a second signal in a second frequency band, a third mixer configured to receive the second signal in the second frequency band, and a fourth mixer configured to receive a third signal in a third frequency band. The system can further include a controller configured to selectively activate one of the first mixer and the second mixer, and selectively activate one of the third mixer and the fourth mixer.

Abstract: A wireless communications transmitter is divided into N binary weighted communication signal processing paths including both fixed and variable gain communication signal processing chains. Specific bit sequences are used to select a combination of fixed and variable gain signal processing paths to adjust to a desired transmitter output power. Alternately, high and low power communication signal processing paths are chosen as needed with the high power communication signal processing path including an odd order harmonic notch filter.

Abstract: Various configurations and arrangements of systems and methods for providing multi-carrier aggregation are described. A system in accordance with the disclosure can include a first mixer configured to receive a first signal in a first frequency band, a second mixer configured to receive a second signal in a second frequency band, a third mixer configured to receive the second signal in the second frequency band, and a fourth mixer configured to receive a third signal in a third frequency band. The system can further include a controller configured to selectively activate one of the first mixer and the second mixer, and selectively activate one of the third mixer and the fourth mixer.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.