Abstract: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Abstract: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Abstract: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Abstract: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Abstract: A signal detector circuit and digital signal receiver implementing the same. In one embodiment the digital signal receiver includes a switch point detector having a detector output and including a transistor array comprising one or more pull-up branches and one or more pull-down branches. A switch point control circuit is coupled to the switch point detector. The switch point control circuit generates branch enable signals for selectively enabling or disabling said one or more pull-up branches and said one or more pull-down branches in a detector output polarity dependent manner.

Abstract: A terminator circuit for use on a pin of an integrated circuit (IC) is disclosed. A preferred embodiment of the present invention includes a clamp circuit that turns on when the voltage at the pin exceeds a threshold value (either an upper or lower bound). Logic and biasing circuitry are used to allow multiple modes of operation by adjusting the threshold values. A particular mode may be selected at any given time so as to strike an appropriate balance between signal quality and power consumption with respect to a particular terminator or set of terminators. This prevents excessive power consumption due to terminator circuitry at inactive or infrequently active IC pins.

Abstract: A terminator circuit for use on a pin of an integrated circuit (IC) is disclosed. A preferred embodiment of the present invention includes a clamp circuit that turns on when the voltage at the pin exceeds a threshold value (either an upper or lower bound). Logic and biasing circuitry are used to allow multiple modes of operation by adjusting the threshold values. A particular mode may be selected at any given time so as to strike an appropriate balance between signal quality and power consumption with respect to a particular terminator or set of terminators. This prevents excessive power consumption due to terminator circuitry at inactive or infrequently active IC pins.