Abstract: An algorithm for detecting a fault in an ECM output signal by determining a status of the output signal, incrementing an error timer and a retry timer when the status is abnormal, incrementing a retry counter when the retry timer reaches a maximum retry time, and reporting an intermittent fault if the retry counter reaches a retry limit before the error timer reaches an error timer maximum.

Abstract: A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link; and de-packetizing the even-sized packets to reform the even number of odd-sized packets. Re-packetizing may involve dividing each of the even number of odd-sized packets into an even-sized portion and a remaining portion. Each even-sized portion may be transferred as one of the even-sized packets. The remaining portions of each of the even number of odd-sized packets may be combined to form another one of even-sized packets. De-packetizing may involve associating each of several portions of one of the even-sized packets with a respective other one of the even-sized packets.

Abstract: Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped region may be verified such that local completion of the write indicates that the mirrored write has also completed. Write requests targeting another mapped region may be unverified. Unverified writes may be verified by performance of a verified write.

Abstract: A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power source. The method further comprises monitoring the level of charge stored in the exhaustible power source. The method further comprises adjusting the storage level of the cache in response to a detected change in the level of charge. In this way, the method ensures that adequate battery power is available to transfer the contents of the cache to a non-volatile data storage medium.

Abstract: A method may involve: receiving a request to perform a block write to a target device and data associated with the block write; buffering the data associated with the block write prior to completing the block write to the target device; storing an indication identifying a block address range of the block write; receiving a request to perform a read to the target device; and determining whether an address of the read is within the block address range of the block write identified by the indication. In some embodiments, such a method may allow the read to complete ahead of the block write dependent on whether the address of the read is within the block address range of the block write identified by the indication.

Abstract: Various embodiments of systems and methods for implementing shared memory regions in a distributed shared memory system may involve implementing several different shared memory regions in each distributed shared memory node. Each node may reflect write access requests targeting those shared memory regions to one or more other nodes, depending on which shared region is targeted (e.g., requests targeting one region may be reflected to a single other node while requests targeting other regions may be reflected to more than one other node). A node's completion of the requested write access locally may be dependent on the completion of the write access in the other nodes, depending on which shared memory region is targeted.

Abstract: Resources may be shared between multiple controllers configured to access those resources by associating a portion of a semaphore shared memory region with each different shared resource. Whenever a local write request to the portion of the semaphore shared memory region is detected by a memory controller, the memory controller may broadcast the write request to other remote memory controllers. The memory controller may delay performing a memory access to a local copy of that portion of the semaphore shared memory region until the other memory controllers have performed the write access to their copy of the semaphore shared memory region. The values stored in the semaphore shared memory region indicate which controller currently has access to the shared resource.

Abstract: A method for operating a data processing system is provided. The method includes receiving a plurality of data segments, and for each of the plurality of data segments, generating an error correction code (ECC) corresponding to the data segment, said ECC providing at least one-bit error correction capability. Finally, an extended parity segment is calculated from the plurality of data segments and the corresponding ECCs, said extended parity segment including a parity segment calculated from the plurality of data segments and a parity ECC calculated from the corresponding ECCs.

Abstract: Each node's memory controller may be configured to send and receive messages on a dedicated memory-to-memory interconnect according to the communication protocol and to responsively perform memory accesses in a local memory. The type of message sent on the interconnect may depend on which memory region is targeted by a memory access request local to the sending node. If certain regions are targeted locally, a memory controller may delay performance of a local memory access until the memory access has been performed remotely. Remote nodes may confirm performance of the remote memory accesses via the memory-to-memory interconnect.

Abstract: A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link; and de-packetizing the even-sized packets to reform the even number of odd-sized packets. Re-packetizing may involve dividing each of the even number of odd-sized packets into an even-sized portion and a remaining portion. Each even-sized portion may be transferred as one of the even-sized packets. The remaining portions of each of the even number of odd-sized packets may be combined to form another one of even-sized packets. De-packetizing may involve associating each of several portions of one of the even-sized packets with a respective other one of the even-sized packets.

Abstract: A method may involve: receiving a request to perform a block write to a target device and data associated with the block write; buffering the data associated with the block write prior to completing the block write to the target device; storing an indication identifying a block address range of the block write; receiving a request to perform a read to the target device; and determining whether an address of the read is within the block address range of the block write identified by the indication. In some embodiments, such a method may allow the read to complete ahead of the block write dependent on whether the address of the read is within the block address range of the block write identified by the indication.

Abstract: Various embodiments of systems and methods for implementing shared memory regions in a distributed shared memory system may involve implementing several different shared memory regions in each distributed shared memory node. Each node may reflect write access requests targeting those shared memory regions to one or more other nodes, depending on which shared region is targeted (e.g., requests targeting one region may be reflected to a single other node while requests targeting other regions may be reflected to more than one other node). A node's completion of the requested write access locally may be dependent on the completion of the write access in the other nodes, depending on which shared memory region is targeted.

Abstract: Resources may be shared between multiple controllers configured to access those resources by associating a portion of a semaphore shared memory region with each different shared resource. Whenever a local write request to the portion of the semaphore shared memory region is detected by a memory controller, the memory controller may broadcast the write request to other remote memory controllers. The memory controller may delay performing a memory access to a local copy of that portion of the semaphore shared memory region until the other memory controllers have performed the write access to their copy of the semaphore shared memory region. The values stored in the semaphore shared memory region indicate which controller currently has access to the shared resource.

Abstract: Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped region may be verified such that local completion of the write indicates that the mirrored write has also completed. Write requests targeting another mapped region may be unverified. Unverified writes may be verified by performance of a verified write.

Abstract: Each node's memory controller may be configured to send and receive messages on a dedicated memory-to-memory interconnect according to the communication protocol and to responsively perform memory accesses in a local memory. The type of message sent on the interconnect may depend on which memory region is targeted by a memory access request local to the sending node. If certain regions are targeted locally, a memory controller may delay performance of a local memory access until the memory access has been performed remotely. Remote nodes may confirm performance of the remote memory accesses via the memory-to-memory interconnect.

Abstract: A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power source. The method further comprises monitoring the level of charge stored in the exhaustible power source. The method further comprises adjusting the storage level of the cache in response to a detected change in the level of charge. In this way, the method ensures that adequate battery power is available to transfer the contents of the cache to a non-volatile data storage medium.

Abstract: A method for operating a data processing system is provided. The method includes receiving a plurality of data segments, and for each of the plurality of data segments, generating an error correction code (ECC) corresponding to the data segment, said ECC providing at least one-bit error correction capability. Finally, an extended parity segment is calculated from the plurality of data segments and the corresponding ECCs, said extended parity segment including a parity segment calculated from the plurality of data segments and a parity ECC calculated from the corresponding ECCs.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system comprises a plurality of nodes an-d a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.