Abstract: This invention discloses a hardware manager and scheduler device which can be implemented within a distributed operating system. The scheduler replaces software synchronization and interaction with two unit-level hardware units that facilitate task scheduling. These units utilize global machine memory to manage scheduling queues using a simple algorithm. The "tasks" managed may be programs requiring execution by a processor, other shared system resources that must be cooperatively scheduled, or input/output queues through system peripheral connections. One unit manages tasks waiting to be executed while the other unit manages tasks which have been completed. Each unit reads and writes pointers to task control blocks stored in a shared memory into and from one or more circular memory queues stored separately in the shared memory. Each queue may correspond to a particular task priority and may be separately managed by the device of this invention.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: The computer system has its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior ad performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: An array processor system is provided with a system to implement a refraction algorithm to prevent incorrect expert system rule firing based on stale or future data, in those production system expert systems which employ content addressable memories for storage of the expert system's facts and its processing control information. The computer system is especially suitable for system which have expert system resources, and there are generic applications of refraction which can be used in any architecture, from scalar to massively parallel, and an associative memory or content addressable memory. The system need not use the RETE algorithm. The computer expert system, has an inference engine and a refraction check mechanism. It is provided with a time stamping mechanism. The computer memory will have working memory elements associated with the processing elements of the array processor. The array processor has a content addressable memory.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: A data processing system is provided with a system to implement a form of data compression--the Ziv-Lempel or Ziv-Lempel-Welsh (ZLW) algorithm--in those systems which incorporate a content addressable memory (CAM), also known as an associative memory. Such implementation results in significant processing performance improvement in the data compression and decompression phases. The ZLW algorithm is widely used in industry and government to realize the reduction in amount of storage space needed for various forms of computer system data files. The processing to result in a LZW compressed file, or the inverse decompress operation, consumes significant computer resources. Such resource and time is justified realizing the savings in amount of computer main and secondary stores needed to retain various data files. The algorithms presented here-in are a significant variation on the basic ZLW theme.

Abstract: Disclosed is a method and multiprocessor apparatus to convert an alphanumeric input into input to an application program as a text processing or word processing program. This is accomplished in a computer having relative motion and/or relative position sensing input capability and a content addressable memory including a comparand register, tag fields, data fields, and a match circuit. The method continuously determines when the relative motion and/or relative position sensing input is active. When the input is active the system senses a basic attribute myotion and/or position of the active relative motion and/or relative position sensing input and defines a meta attribute of the sensed input. Exemplary meta attributes include the turns, weighted input center, and stroke geometry and topology.