Abstract: A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.

Abstract: A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.

Abstract: A method of requesting data in a data processing system has the steps of receiving a plurality of requests for data by a request arbitrator (12) from a plurality of requesters (REQUESTER A, REQUESTER B, REQUESTER C), requesting a first portion of each request at a first time and requesting a second portion of each request at a second time. Each of the requests for data corresponds to a first portion of data. At least one of the requests also corresponds to a second portion of data. The first portions and second portion are requested according to a first and to a second predetermined order, respectively. The disclosed method requests a critical mount of data first for each request before any non-critical data portions are requested.

Abstract: A method of transferring error correcting code has the steps of receiving a first data stream in a data processing system, generating a second data stream, and generating a correctable error signal. Initially, the data processing system outputs the first data stream. Later, the data processing system may select the second data stream to output responsive to a first predetermined transition of the correctable error signal. The second data stream and the correctable error signal are generated from the first data stream pursuant to an error correcting code protocol. The disclosed method permits high speed pipelined data processor operation.

Abstract: A TTL to CML input buffer and conversion apparatus having a Schmitt trigger to receive a TTL logic signal and apply the logic signal levels to a CML gate unit. The logic levels of the TTL signal are converted by the CML gate unit into CML logic signals.

Abstract: A voltage reference generator based on a pair of differentially connected transistor devices, having a current sink at that connection, with one leg of the differential pair adapted for connection to a first voltage and the other leg having a pair of series-connected impedances connected thereto and adapted at the opposite end for connection to a second voltage supply.