Patents by Inventor John D. Cuthbert

John D. Cuthbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit process using a "hard mask"
    Patent number: 5264076
    Abstract: A layer of spin-on-glass is used as a hard mask for patterning an underlying layer of polysilicon. The patterned polysilicon may be used in the gate structures of field effect transistors.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: November 23, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: John D. Cuthbert, David P. Favreau
  • Semiconductor device fabrication including a non-destructive method for examining lithographically defined features
    Patent number: 4788117
    Abstract: A non-destructive double exposure method of examining photoresist features in section by, e.g., scanning electron microscopy, is described.
    Type: Grant
    Filed: January 28, 1987
    Date of Patent: November 29, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: John D. Cuthbert, Dennis E. Schrope, Tungsheng Yang
  • Removal of coating from periphery of a semiconductor wafer
    Patent number: 4510176
    Abstract: The specification describes techniques for removing the edge bead region from a coated semiconductor wafer by directing a jet of solvent at the wafer periphery while the wafer is spinning. The flow patterns of debris resulting from this removal are controlled to prevent contamination of the chip sites on the wafer.
    Type: Grant
    Filed: September 26, 1983
    Date of Patent: April 9, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: John D. Cuthbert, Nicholas A. Soos
  • Dynamic random access memory
    Patent number: 4240195
    Abstract: A memory in which each cell comprises an MOS transistor merged with a storage capacitor and in which the cells are arranged to permit adjacent pairs of transistors in a common column to share a common source and the transistors in a common row to share a common gate electrode conductor. The memory uses a first polycrystalline silicon layer which is patterned to provide interconnected storage electrodes and a second polycrystalline silicon layer which is patterned to provide a plurality of stripes to serve as the bit sense lines and a plurality of gate electrodes.
    Type: Grant
    Filed: September 15, 1978
    Date of Patent: December 23, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: James T. Clemens, John D. Cuthbert, Frank J. Procyk, George M. Trout