Abstract: A multi-processor computer system comprises one or more CPUs (1) connected to a host computer (2) via a common PCI bus system backplane (3). The host computer (2) comprises a host microprocessor and associated memory unit and each CPU comprises a local microprocessor (5) having a local bus (15), an associated local memory unit (6), and a PCI connector (9) connected to the PCI backplane. Each CPU (1) further comprises a bridge (7) having at least two decoders installed between the CPU local bus (15) and the PCI connector (9) and providing an interface between the local microprocessor (5) and the associated local memory unit (6). A first decoder (A) of each bridge (7) is programmed to a first address range for access to the respective local memory unit (6) by the associated local processor (5), and a second decoder (B) of each bridge (7) is programmed to a second address range for access to the same physical memory of the memory unit (6) by another microprocessor (5) of the system.