Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed.

Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed.