Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.

Abstract: A pre-amplifier, a Thevenin writer and a disk drive employing transistors having a breakdown voltage below a circuitry operating voltage. In one embodiment, the pre-amplifier includes an emitter-follower transistor pair couplable to a power supply and a differential transistor pair, having a collector-emitter breakdown voltage below a voltage of the power supply, that receives current from, and controlled by, the emitter-follower transistor pair.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Abstract: A disk driver writer precompensation system modulates the write current waveform based on a pattern of data bits magnetically recorded on a medium in order to adjust the timing of magnetic transitions recorded on the medium.

Abstract: A preamplifier system is connected through an interconnect to a read head. The preamplifier system includes a voltage-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output, and also includes a current-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output. A summing circuit is connected to combine the outputs of the voltage-sense preamplifier and the current-sense preamplifier. For optimal performance, the preamplifier system is impedance matched to the interconnect. The preamplifier system achieves excellent response due to impedance matching with acceptably low noise levels, since the correlated noise associated with the current-sense preamplifier is canceled at the summing circuit.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

Abstract: A pre-amplifier, a Thevenin writer and a disk drive employing transistors having a breakdown voltage below a circuitry operating voltage. In one embodiment, the pre-amplifier includes an emitter-follower transistor pair couplable to a power supply and a differential transistor pair, having a collector-emitter breakdown voltage below a voltage of the power supply, that receives current from, and controlled by, the emitter-follower transistor pair.

Abstract: A disk driver writer precompensation system modulates the write current waveform based on a pattern of data bits magnetically recorded on a medium in order to adjust the timing of magnetic transitions recorded on the medium.

Abstract: A write circuit selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect.

Abstract: A pulse-mode data writing protocol is disclosed which reduces the time required to implement a transition in the direction of magnetization of a recording medium, and which reduces the total power required to encode a given data sequence. After a magnetic transition is encoded on the medium by generating a write current pulse through the write head, the write current through the recording head is reduced, thereby utilizing the spatial extent of the write bubble to encode the lack of a transition on the medium. Alternate configurations are disclosed for various scenarios of write bubble size versus maximum cell size, all utilizing the principle of the invention.

Abstract: A plurality of data bits are magnetically recorded on a medium (such as a magnetic disk in a disk drive system) by creating a write bubble region encroaching on the medium. The write bubble region has a magnetic polarity that is reversed in a pattern that corresponds to the values of the data bits being recorded on the medium. The timing of the reversing of the magnetic polarity of the write bubble region is adjusted by a precompensation system to ensure that the recorded data bits are evenly spaced on the medium. The timing adjustment is made by the precompensation system based on a state of at least one data bit previously recorded on the medium and on a state of at least one data bit to be subsequently recorded on the medium.

Abstract: A preamplifier system is connected through an interconnect to a read head. The preamplifier system includes a voltage-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output, and also includes a current-sense preamplifier having at least one input connected through the interconnect to the read head and having at least one output. A summing circuit is connected to combine the outputs of the voltage-sense preamplifier and the current-sense preamplifier. For optimal performance, the preamplifier system is impedance matched to the interconnect. The preamplifier system achieves excellent response due to impedance matching with acceptably low noise levels, since the correlated noise associated with the current-sense preamplifier is canceled at the summing circuit.

Abstract: A write driver for an inductive load includes load terminals for connection to an inductive load, and an impedance-matched driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. The inductive load includes an inductive write head and a transmission line of predetermined impedance connected to the write head for connection to the first and second load terminals. Ringing is suppressed by the impedance-matching of the driver circuit to the transmission line connecting the load to the terminals.

Abstract: A read system for reading information from a storage medium and for providing an output signal to circuitry external from the read system is disclosed. The read system includes individual channel circuitry, a bias current generator for providing a bias current to the read system, and preamplifier circuitry connected between the bias current generator and the individual channel circuitry. The individual channel circuitry further includes a first and a second magnetoresistive element, a first and a second transistor, and a first and a second switch. The preamplifier circuit further includes a first and a second capacitor connected between a low potential and the first and second switches, respectively, and a third capacitor connected between the first and second capacitors. The preamplifier also includes a first and a second operational amplifier having an output connected to a base of the first transistor and a base of the second transistor.

Abstract: Echo cancellation is provided in a disk drive circuit having a transducing head connected to a preamplifier circuit by an electrical interconnect with a first time delay, a first interface between the preamplifier and the electrical interconnect having a first reflection coefficient and a second interface between the transducing head and the electrical interconnect having a second reflection coefficient. The echo cancellation technique delays a preamplifier output signal with a second time delay, the second time delay being double the first time delay. The preamplifier output signal is also filtered so as to simulate the effects of the first and second reflection coefficients. The delayed and filtered signal is then subtracted from the preamplifier output signal, thereby removing echo content from the signal.

Abstract: A voltage boost circuit for a write driver includes first and second semiconductor devices, such as Schottky diodes, coupled to respective first and second nodes to conduct write current through respective first or second current switches of the write driver when a forward voltage across the respective first or second semiconductor device exceeds a design voltage. The first and second current switches are responsive to respective complementary first and second input signals to direct write current in opposite directions through the winding between the first and second nodes. First and second storage devices are connected to the respective first and second semiconductor devices, and first and second buffers are responsive to a first state of the respective first and second input signals to operate the respective first or second storage device to increase the forward voltage across the respective first or second semiconductor device.

Abstract: A write driver for an inductive load includes load terminals for connection to an inductive load, and a driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. A voltage-mode H-bridge connected to the load terminals is operable to selectively supply a voltage across the load terminals and head. Program means operates the voltage-mode H-bridge for a predetermined time period following initiation of the respective first and second control signal to provide a voltage across the load terminals which quickly raises the write current to a steady state condition. Ringing is suppressed by employing an impedance-matched H-bridge for the driver circuit, the impedance-matched H-bridge having an impedance matched to the impedance of a transmission line connecting the load to the terminals.

Abstract: A power supply filter has a primary current source coupled to a node carrying a power supply signal. The second end of the primary current source is coupled to an impedance that is further coupled to a low voltage node. A differential amplifier having an inverting input, a non-inverting input, and an output, has its non-inverting input coupled to the junction between the impedance and the primary current source. The output of the differential amplifier carries the filtered power supply signal and is coupled to a capacitance. The capacitance is coupled between the output and a lower voltage. A feedback path is coupled between the output and the inverting input.