Patents by Inventor John D. Moran

John D. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8501612
    Abstract: A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: John D. Moran, Blanca Kruse, Amilcar B. Gamez Sanchez
  • Patent number: 7820473
    Abstract: A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A stacked structure is formed on a portion of the guard ring and a portion of the epitaxial layer. The stacked structure includes a layer of semi-insulating semiconductor material disposed on a layer of dielectric material. A first metal layer is formed on the portion of the epitaxial layer adjacent a first side of the stacked structure and on a first portion of the stacked structure. A second metal layer is formed on the portion of the epitaxial layer adjacent a second side of the stacked structure and on a second portion of the stacked structure.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Linghui Chen, Blanca Estela Kruse, Mark Duskin, John D. Moran
  • Publication number: 20090079093
    Abstract: A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 26, 2009
    Inventors: John D. Moran, Blanca Kruse, Amilcar B. Gamez Sanchez
  • Patent number: 5773368
    Abstract: A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: June 30, 1998
    Assignee: Motorola, Inc.
    Inventor: John D. Moran
  • Patent number: 5075259
    Abstract: Semiconductor device structures having very smooth surfaces and very high doping levels of opposite types present on the same wafer may be plated in the same electroless plating bath without differentiation between the N and P regions or rough and smooth surface regions. This is achieved by a pre-treatment involving coating the wafer surface with a metal salt (e.g., NiCl in glycol and water) and reducing the metal salt in an oxygen free atmosphere (e.g., hydrogen) at a temperature (e.g., >300.degree. C. for Si) sufficient to promote formation of an intermetallic between the reduced metal and the semiconductor substrate. This provides very uniform and effective nucleation sites for the subsequent electroless plating process irrespective of the smoothness, doping type and doping density of the semiconductor surface.
    Type: Grant
    Filed: August 22, 1989
    Date of Patent: December 24, 1991
    Assignee: Motorola, Inc.
    Inventor: John D. Moran
  • Patent number: 4977107
    Abstract: Rectifiers of excellent characteristics may be more economically fabricated by a process in which a cavity is first etched in a non-epitaxial semiconductor wafer to a depth in the range of typically 15-25 percent of the initial wafer thickness. Simultaneous diffusion of N and P type dopants is used to provide (for an N type substrate) a P+ region in the bottom of the cavity and surrounding surface, and an N+ region on the opposite face of the wafer. A mask is then provided in the cavity bottom and the surrounding wafer regions etched to remove the P+ dopant outside the cavity thereby re-exposing the surrounding region of the original N type substrate. The P+ region may be level with or protrude slightly from the substrate surface. The junction formed between the P+ region in the cavity bottom and the N type substrate has a gradual contour where it intersects the surface thereby providing a more favorable field distribution. Passivation and metallization are provided in the conventional manner.
    Type: Grant
    Filed: August 23, 1989
    Date of Patent: December 11, 1990
    Assignee: Motorola Inc.
    Inventor: John D. Moran
  • Patent number: 3967502
    Abstract: A thermal timing device formed by a meat thermometer provided with a removable heat insulating shroud or jacket. The meat thermometer may be used in the usual fashion without the jacket to indicate the extent to which meat is roasted. With the jacket in place on the thermometer, the timing device may then be used for controlling other cooking processes such as broiling, baking, deep fat frying, and boiling.
    Type: Grant
    Filed: September 6, 1974
    Date of Patent: July 6, 1976
    Inventor: John D. Moran