Abstract: A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data lengths. The memory interface (28) includes an address register (50, 52) for receiving addressing information to access the memory (12). A mode bit (80) and a high/low bit (82) in the address register (50, 52) determine the different operating modes of the memory interface (28).

Abstract: An asynchronous latch including a finite state machine (301) and a level-sensitive latch (304) in a feedback path of the finite state machine. The input to the level-sensitive latch (304) is a signal generated by decoding the state of the finite state machine (301). The level-sensitive latch output is fed back to the finite state machine inputs to control next-state transitions. An asynchronous input line couples an asynchronous signal to the level-sensitive latch so that the asynchronous signal is used as a latching signal.

Abstract: A maximum-likelihood sequence estimator receiver includes a matched filter connected to a digital transmission channel and a sampler for providing sampled signals output by the matched filter. The sampled signals are input to an analog neural network to provide high-speed outputs representative of the transmission channel signals. The neural network outputs are also provided as inputs to a coefficient estimator which produces coefficients for feedback to the matched filter. For time-varying transmission channel characteristics, the coefficient estimator provides a second coefficient output which is utilized for changing the interconnection strengths of the neural network connection matrix to offset the varying transmission channel characteristics.

Abstract: A dual detector spectroscopic endpoint determination system is used which has dual channels that enables the combination of channels to increase gain, cancel out background noise, and to use either one or more spectroscopic channels.