Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.

Abstract: A Zener diode—capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.

Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.

Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.

Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

Abstract: An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.

Abstract: A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.

Abstract: An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.

Abstract: Larger ceramic chip capacitors are reliably mounted with minimal risk of flexure induced cracking on circuit boards by adding terminal extensions to one face of the capacitor and soldering across all or part of the extensions. A ball grid array is preferred.

Abstract: A multi-layer capacitor with reduced ESL and internal electrodes for same. The multi-layer capacitor has a monolithic capacitor body with first polarity external electrodes and second polarity external electrodes on an exterior of the body. A first internal electrode has first diverging lead-out electrodes in electrical contact with the first polarity external electrodes. A second internal electrode has second diverging lead-out electrodes in electrical contact with the second polarity external electrodes. The first internal electrode and the second internal electrode are in parallel spaced-apart relationship with a dielectric there between.

Abstract: A ceramic capacitor with a low-profile leadframe. The ceramic capacitor comprises a multiplicity of parallel plates in planar relationship. Each plate terminates at opposing faces in an alternating pattern. A dielectric is between the parallel plates. Two external terminations are on opposing sides of the capacitor wherein each external termination is in electrical contact with alternating plates of the multiplicity of parallel plates. The bottom half of the ceramic capacitor including the external terminations is treated with an insulative coating prior to attachment to a leadframe. The noninsulated portions of the terminations are attached to the leadframe and the insulator prevents the leadframe from attaching to the lower vertical faces of the terminations. The leadframe in this manner creates no excessive distance between the chip and the PCB surface, thus reducing inductance and resistance.

Abstract: A multi-layer capacitor with reduced ESL and internal electrodes for same. The multi-layer capacitor has a monolithic capacitor body with first polarity external electrodes and second polarity external electrodes on an exterior of the body. A first internal electrode has first diverging lead-out electrodes in electrical contact with the first polarity external electrodes. A second internal electrode has second diverging lead-out electrodes in electrical contact with the second polarity external electrodes. The first internal electrode and the second internal electrode are in parallel spaced-apart relationship with a dielectric there between.

Abstract: The present invention relates to improvements in ceramic monolithic capacitors and is directed more specifically to a low value, low loss capacitor especially adapted for use in high frequency applications. The capacitor is characterized in that the same includes two electrode layers, namely a surface electrode mounted on an end portion of the monolith and an internal electrode which extends across the entire cross section of the monolith in spaced parallel relation to the surface electrode. Termination is effected to the internal electrode about the entire periphery of the monolith, and to the surface electrode preferably over substantially the entire area of the surface electrode.