Patents by Inventor John D. Redden

John D. Redden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrical conduction array on the bottom side of a tester thermal head
    Patent number: 6784668
    Abstract: An apparatus for testing an electrical device which includes fuses has a resilient, compressive, insulating base amounted to the underside of a thermal head. A plurality of conductive elements are mounted to the base in parallel relation. A number of these conductive elements are caused to be brought into contact with and bridge a fuse of the device when the thermal head is brought in dose proximity to the device. The conductive elements cause the fuse to be bridged, so that connection is provided between one side of the fuse and the other.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: August 31, 2004
    Assignee: Advanced Micro Devices Inc.
    Inventors: Donald L. Lambert, John D. Redden
  • Packaging tray
    Patent number: 6345720
    Abstract: A packaging tray includes a base member, first and second side members, and a first top member. The base member has a first plurality of channels defined therein. The first and second side members extend from the base and are rotatable with respect to the base. The first top member extends from one of the first and second side members and is rotatable with respect to the one of the first and second side members. The first top member includes a second plurality of channels defined therein. The first plurality of channels are aligned with the second plurality of channels.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: February 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John D. Redden, Allan M. Fetty, Richard M. Greig
  • Interlocking and invertible semiconductor device tray and test contactor mating thereto
    Patent number: 5492223
    Abstract: A tray (10') for handling a semiconductor device encapsulated in a package body and having multiple electrical I/Os projecting from the package body has cell-to-cell interlocking capability as well as invertibility. An interlocking nest feature (16) is formed on the underside of the tray and interfaces with the cells (12') on the topside of the tray (10') when the trays are stacked. The interlocking nest feature has an external chamfer (20) which mates with a lead-in chamfer (18) of the tray cell to align the interlocking feature (16) and the cell (12'). The interlocking nest feature (16) has an internal device retaining chamfer (22) and a device capture surface (26) to guide and retain the semiconductor device when stacking trays, inverting trays or processing semiconductor devices with the trays inverted. In-tray inspection and electrical test are also possible using a test contactor having a functional equivalent of the interlocking nest feature.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: February 20, 1996
    Assignee: Motorola, Inc.
    Inventors: Keith A. Boardman, John D. Redden