Abstract: Systems and methods are provided to implement a state map to control operations of a complementary metal-oxide-semiconductor (CMOS) sensor. The state map can be a table comprising one or more locations. Each of the locations can comprise a destination state to define the operations of the sensor and an exit criterion to advance to a next location in the state map. For example, an operation sequence can be implemented using the state map to instruct the CMOS sensor to perform a specific set of operations. Further, a data value to represent the destination state and/or a variable input can be stored in a writable address of a register. Thus, a simplified architecture can be provided to implement CMOS sensor operation states, for instance, to improve interactions between real time and non-real time signals and to increase functionality of the CMOS sensor.

Abstract: Programmable data readout for optical image sensors is disclosed herein. By way of example, vertical skipping and vertical mixing functionality is provided that is responsive to commands, enabling dynamic selectivity and processing of optical sensor data. A data output control system can be incorporated with or coupled to data readout circuitry of an optical sensor. The output control system comprises a vertical skipping engine that can dynamically select a subset of data for output in response to one or more skipping commands, and a vertical mixing engine that can act upon subsets of data in accordance with processing functions called by respective mixing commands. The disclosure provides simplification of selective data readout and processing for image sensors, potentially reducing design, testing, and maintenance overhead, as well as cost and number of integrated circuit components.

Abstract: Systems and methods are provided to implement a state map to control operations of a complementary metal-oxide-semiconductor (CMOS) sensor. The state map can be a table comprising one or more locations. Each of the locations can comprise a destination state to define the operations of the sensor and an exit criterion to advance to a next location in the state map. For example, an operation sequence can be implemented using the state map to instruct the CMOS sensor to perform a specific set of operations. Further, a data value to represent the destination state and/or a variable input can be stored in a writable address of a register. Thus, a simplified architecture can be provided to implement CMOS sensor operation states, for instance, to improve interactions between real time and non-real time signals and to increase functionality of the CMOS sensor.

Abstract: Programmable data readout for optical image sensors is disclosed herein. By way of example, vertical skipping and vertical mixing functionality is provided that is responsive to commands, enabling dynamic selectivity and processing of optical sensor data. A data output control system can be incorporated with or coupled to data readout circuitry of an optical sensor. The output control system comprises a vertical skipping engine that can dynamically select a subset of data for output in response to one or more skipping commands, and a vertical mixing engine that can act upon subsets of data in accordance with processing functions called by respective mixing commands. The disclosure provides simplification of selective data readout and processing for image sensors, potentially reducing design, testing, and maintenance overhead, as well as cost and number of integrated circuit components.

Abstract: The claimed subject matter provides systems and/or methods that facilitate controlling timing dependencies in a mixed signal circuit. Timing performance associated with a horizontal scanner and an analog to digital converter (ADC) can be monitored. Moreover, data related to the monitored timing performance can be leveraged to modify timing parameter(s) of clocks that coordinate operations of the horizontal scanner and the ADC (e.g., and/or digital component(s) included in the mixed signal circuit). For example, the clocks associated with the horizontal scanner and the ADC can be independently tuned to optimize mixed signal circuit performance.

Abstract: The claimed subject matter provides systems and/or methods that facilitate controlling timing dependencies in a mixed signal circuit. Timing performance associated with a horizontal scanner and an analog to digital converter (ADC) can be monitored. Moreover, data related to the monitored timing performance can be leveraged to modify timing parameter(s) of clocks that coordinate operations of the horizontal scanner and the ADC (e.g., and/or digital component(s) included in the mixed signal circuit). For example, the clocks associated with the horizontal scanner and the ADC can be independently tuned to optimize mixed signal circuit performance.

Abstract: A data switch includes multiple switching modules interconnected over a backplane. The data switch maintains flow integrity while path transitioning. The flow integrity can be maintained by temporarily disabling one or more of the switching modules from transmitting data units over the backplane for a flow undergoing a path transition. The disable condition is imposed when the path transition is commenced, and is lifted after the path transition is completed and an interval has passed ensuring that all data units for the flow transmitted to the backplane prior to imposing the disable condition have cleared the backplane. The backplane includes a multicast fabric and a unicast fabric, wherein flow path transitions are made from the multicast fabric to the unicast fabric upon source learning. All switching modules are temporarily disabled from transmitting data units having as a destination address an address undergoing source learning to the backplane.

Abstract: An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.