Patents by Inventor John Danskin
John Danskin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9727463Abstract: A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set of rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data.Type: GrantFiled: October 14, 2015Date of Patent: August 8, 2017Assignee: Nvidia CorporationInventor: John Danskin
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Publication number: 20160342513Abstract: A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data.Type: ApplicationFiled: October 14, 2015Publication date: November 24, 2016Inventor: John Danskin
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Patent number: 8237705Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.Type: GrantFiled: October 10, 2011Date of Patent: August 7, 2012Assignee: NVIDIA CorporationInventors: John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon S. Moy, Sean Jeffrey Treichler, Brett W. Coon, David Kirk, John Danskin
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Publication number: 20120026175Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.Type: ApplicationFiled: October 10, 2011Publication date: February 2, 2012Applicant: NVIDIA CorporationInventors: John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon S. Moy, Sean Jeffrey Treichler, Brett W. Coon, David Kirk, John Danskin
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Patent number: 8077174Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.Type: GrantFiled: November 1, 2007Date of Patent: December 13, 2011Assignee: NVIDIA CorporationInventors: John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon S. Moy, Sean Jeffrey Treichler, Brett W. Coon, David Kirk, John Danskin
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Publication number: 20080143730Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.Type: ApplicationFiled: November 1, 2007Publication date: June 19, 2008Applicant: NVIDIA CorporationInventors: John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon S. Moy, Sean Jeffrey Treichler, Brett W. Coon, David Kirk, John Danskin
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Publication number: 20070159488Abstract: A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. The pixel distribution logic selects one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area. The processing clusters can be mapped directly to the frame buffers partitions without a crossbar so that pixel data is delivered directly from the processing cluster to the appropriate frame buffer partitions.Type: ApplicationFiled: December 15, 2006Publication date: July 12, 2007Applicant: NVIDIA CorporationInventors: John Danskin, John Montrym, John Lindholm, Steven Molnar, Mark French
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Publication number: 20060132491Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.Type: ApplicationFiled: December 20, 2004Publication date: June 22, 2006Applicant: NVIDIA CorporationInventors: Duncan Riach, John Danskin, Jonah Alben, Michael Ogrinc, Anthony Tamasi