Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.