Abstract: Aspects relate to improved optically black reference pixels in a CMOS iSoc sensor. A system can include a pointer P1 that indicates pixels to be read out during a readout time interval, a pointer P2 that indicates pixels to be reset during the time interval, and a pointer P3 that preserves a validity of a frame. The system also includes a pointer P4 configured to mitigate an integration time of column fixed pattern noise (FPN) rows independently of the integration time of other rows. In some aspects, pointer P4 can mitigate blooming into sampled rows from surrounding rows. Pointer P4 can be continuously rotated, in an aspect. Further, in some aspects, pointer P4 can jump on a second cycle to arrive one line before pointer P1.

Abstract: Aspects relate to improved optically black reference pixels in a CMOS iSoc sensor. A system can include a pointer P1 that indicates pixels to be read out during a readout time interval, a pointer P2 that indicates pixels to be reset during the time interval, and a pointer P3 that preserves a validity of a frame. The system also includes a pointer P4 configured to mitigate an integration time of column fixed pattern noise (FPN) rows independently of the integration time of other rows. In some aspects, pointer P4 can mitigate blooming into sampled rows from surrounding rows. Pointer P4 can be continuously rotated, in an aspect. Further, in some aspects, pointer P4 can jump on a second cycle to arrive one line before pointer P1.

Abstract: Systems and methods are provided that facilitate mitigating column gain mismatch in a CMOS imaging System-on-Chip (iSoC) sensor. Tunable voltages that mimic presence of photo-charge can be provided to test pixels in one or more rows of a pixel array. Moreover, column-specific digital gain corrections can be calibrated based upon input data received from the test pixels. During calibration, actual data can be compared to a target expected to be obtained via an analog readout architecture. The calibrated, column-specific digital gain corrections can be utilized to correct for column gain mismatch to yield output data. Further, correction values corresponding to the column-specific digital gain corrections can be retained in and retrieved from memory. The correction values, for example, can be a function of a scaling parameter that is tuned to match an available memory dynamic to a range of uncorrected gain mismatch.

Abstract: Systems and methods are provided that facilitate mitigating column gain mismatch in a CMOS imaging System-on-Chip (iSoC) sensor. Tunable voltages that mimic presence of photo-charge can be provided to test pixels in one or more rows of a pixel array. Moreover, column-specific digital gain corrections can be calibrated based upon input data received from the test pixels. During calibration, actual data can be compared to a target expected to be obtained via an analog readout architecture. The calibrated, column-specific digital gain corrections can be utilized to correct for column gain mismatch to yield output data. Further, correction values corresponding to the column-specific digital gain corrections can be retained in and retrieved from memory. The correction values, for example, can be a function of a scaling parameter that is tuned to match an available memory dynamic to a range of uncorrected gain mismatch.