Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Abstract: One embodiment of the present method and apparatus for data stream alignment support includes retrieving a first input from a first register file, retrieving a second input from a second register file, the second register file being dedicated to a stream shift unit and performing the stream shift instruction in accordance with the first input, the second input and a third input.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

Abstract: Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Abstract: Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

Abstract: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

Abstract: A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage.

Abstract: A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.